Patents by Inventor Theodore S. Moise
Theodore S. Moise has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8723241Abstract: A planar integrated MEMS device has a piezoelectric element on a dielectric isolation layer over a flexible element attached to a proof mass. The piezoelectric element contains a ferroelectric element with a perovskite structure formed over an isolation dielectric. At least two electrodes are formed on the ferroelectric element. An upper hydrogen barrier is formed over the piezoelectric element. Front side singulation trenches are formed at a periphery of the MEMS device extending into the semiconductor substrate. A DRIE process removes material from the bottom side of the substrate to form the flexible element, removes material from the substrate under the front side singulation trenches, and forms the proof mass from substrate material. The piezoelectric element overlaps the flexible element.Type: GrantFiled: July 19, 2013Date of Patent: May 13, 2014Assignee: Texas Instruments IncorporatedInventors: Kezhakkedath R. Udayakumar, Marie Denison, Theodore S. Moise
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Publication number: 20130307375Abstract: A planar integrated MEMS device has a piezoelectric element on a dielectric isolation layer over a flexible element attached to a proof mass. The piezoelectric element contains a ferroelectric element with a perovskite structure formed over an isolation dielectric. At least two electrodes are formed on the ferroelectric element. An upper hydrogen barrier is formed over the piezoelectric element. Front side singulation trenches are formed at a periphery of the MEMS device extending into the semiconductor substrate. A DRIE process removes material from the bottom side of the substrate to form the flexible element, removes material from the substrate under the front side singulation trenches, and forms the proof mass from substrate material. The piezoelectric element overlaps the flexible element.Type: ApplicationFiled: July 19, 2013Publication date: November 21, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kezhakkedath R. Udayakumar, Marie Denison, Theodore S. Moise
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Patent number: 8093070Abstract: A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.Type: GrantFiled: February 15, 2007Date of Patent: January 10, 2012Assignee: Texas Instruments IncorporatedInventors: Francis Gabriel Celii, Kezhakkedath R. Udayakumar, Gregory B. Shinn, Theodore S. Moise, Scott R. Summerfelt
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Patent number: 7985603Abstract: A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.Type: GrantFiled: February 4, 2008Date of Patent: July 26, 2011Assignee: Texas Instruments IncorporatedInventors: Francis Gabriel Celii, Robert Kraft, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Theodore S. Moise
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Patent number: 7935543Abstract: One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectric cores during cooling.Type: GrantFiled: May 26, 2009Date of Patent: May 3, 2011Assignee: Texas Instruments IncorporatedInventors: Theodore S. Moise, IV, Scott R. Summerfelt, Kezhakkedath R. Udayakumar
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Patent number: 7723199Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.Type: GrantFiled: January 31, 2007Date of Patent: May 25, 2010Assignee: Texas Instruments IncorporatedInventors: Yaw S. Obeng, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Sanjeev Aggarwal, Francis Gabriel Celii, Lindsey H. Hall, Robert Kraft, Theodore S. Moise
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Publication number: 20090233382Abstract: One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectric cores during cooling.Type: ApplicationFiled: May 26, 2009Publication date: September 17, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Theodore S. Moise, IV, Scott R. Summerfelt, K.R. Udayakumar
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Publication number: 20090194801Abstract: A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.Type: ApplicationFiled: February 4, 2008Publication date: August 6, 2009Applicant: Texas Instruments Inc.Inventors: Francis Gabriel Celii, Robert Kraft, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Theodore S. Moise
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Patent number: 7514734Abstract: Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.Type: GrantFiled: September 6, 2005Date of Patent: April 7, 2009Assignee: Texas Instruments IncorporatedInventors: Sanjeev Aggarwal, Kelly J. Taylor, Theodore S. Moise
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Patent number: 7361599Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.Type: GrantFiled: June 6, 2005Date of Patent: April 22, 2008Assignee: Texas Instruments IncorporatedInventors: Theodore S. Moise, Guoqiang Xing, Mark Visokay, Justin F. Gaynor, Stephen R. Gilbert, Francis Celii, Scott R. Summerfelt, Luigi Colombo
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Publication number: 20080081380Abstract: A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.Type: ApplicationFiled: February 15, 2007Publication date: April 3, 2008Inventors: Francis Gabriel Celii, Kezhakkedath R. Udayakumar, Gregory B. Shinn, Theodore S. Moise, Scott R. Summerfelt
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Publication number: 20070298521Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.Type: ApplicationFiled: January 31, 2007Publication date: December 27, 2007Applicant: Texas Instruments IncorporatedInventors: Yaw S. Obeng, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Sanjeev Aggarwal, Francis Gabriel Celii, Lindsey H. Hall, Robert Kraft, Theodore S. Moise
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Patent number: 7220600Abstract: Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching (140, 200) portions of an upper electrode, etching (141, 201) ferroelectric material, and etching (142, 202) a lower electrode to define a patterned ferroelectric capacitor structure, and etching (143, 206) a portion of a lower electrode diffusion barrier structure. The methods further comprise ashing (144, 203) the patterned ferroelectric capacitor structure using a first ashing process, performing (145, 204) a wet clean process after the first ashing process, and ashing (146, 205) the patterned ferroelectric capacitor structure using a second ashing process directly after the wet clean process at a high temperature in an oxidizing ambient.Type: GrantFiled: December 17, 2004Date of Patent: May 22, 2007Assignee: Texas Instruments IncorporatedInventors: Scott R. Summerfelt, Lindsey H. Hall, Kezhakkedath R. Udayakumar, Theodore S. Moise, IV
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Patent number: 7183602Abstract: Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.Type: GrantFiled: January 11, 2005Date of Patent: February 27, 2007Assignee: Texas Instruments IncorporatedInventors: K. R. Udayakumar, Theodore S. Moise, Scott R. Summerfelt
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Patent number: 7019352Abstract: Semiconductor devices and fabrication methods are disclosed, in which one or more low silicon-hydrogen SiN barriers are provided to inhibit hydrogen diffusion into ferroelectric capacitors and into transistor gate dielectric interface areas. The barriers may be used as etch stop layers in various levels of the semiconductor device structure above and/or below the level at which the ferroelectric capacitors are formed so as to reduce the hydrogen related degradation of the switched polarization properties of the ferroelectric capacitors and to reduce negative bias temperature instability in the device transistors.Type: GrantFiled: August 7, 2003Date of Patent: March 28, 2006Assignee: Texas Instruments IncorporatedInventors: K. R. Udayakumar, Martin G. Albrecht, Theodore S. Moise, Scott R. Summerfelt, Sarah I. Hartwig
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Patent number: 7001821Abstract: Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.Type: GrantFiled: November 10, 2003Date of Patent: February 21, 2006Assignee: Texas Instruments IncorporatedInventors: Sanjeev Aggarwal, Kelly J. Taylor, Theodore S. Moise
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Patent number: 6984857Abstract: Semiconductor devices and fabrication methods are presented, in which a hydrogen barrier is provided above a ferroelectric capacitor to prevent degradation of the ferroelectric material during back-end manufacturing processes employing hydrogen. The hydrogen barrier comprises silicon rich silicon oxide or amorphous silicon, which can be used in combination with an aluminum oxide layer to inhibit diffusion of process-related hydrogen into the ferroelectric capacitor layer.Type: GrantFiled: July 16, 2003Date of Patent: January 10, 2006Assignee: Texas Instruments IncorporatedInventors: K. R. Udayakumar, Martin G. Albrecht, Theodore S. Moise, IV, Scott R. Summerfelt, Sanjeev Aggarwal, Jeff L. Large
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Patent number: 6982448Abstract: Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.Type: GrantFiled: March 18, 2004Date of Patent: January 3, 2006Assignee: Texas Instruments IncorporatedInventors: K. R. Udayakumar, Theodore S. Moise, Scott R. Summerfelt
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Patent number: 6902939Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.Type: GrantFiled: August 19, 2002Date of Patent: June 7, 2005Assignee: Texas Instruments IncorporatedInventors: Theodore S. Moise, Guoqiang Xing, Mark Visokay, Justin F. Gaynor, Stephen R. Gilbert, Francis Celii, Scott R. Summerfelt, Luigi Colombo
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Patent number: 6876021Abstract: The present invention forms sidewall diffusion barrier layer(s) that mitigate hydrogen contamination of ferroelectric capacitors. Sidewall diffusion barrier layer(s) of the present invention are formed via a physical vapor deposition process at a low temperature. By so doing, the sidewall diffusion barrier layer(s) are substantially amorphous and provide superior protection against hydrogen diffusion than conventional and/or crystalline sidewall diffusion barrier layers.Type: GrantFiled: November 25, 2002Date of Patent: April 5, 2005Assignee: Texas Instruments IncorporatedInventors: J. Scott Martin, Scott R. Summerfelt, Theodore S. Moise, Kelly J. Taylor, Luigi Colombo, Sanjeev Aggarwal, Sirisha Kuchimanchi, K. R. Udayakumar, Lindsey Hall