Abstract: A ferroelectric memory device comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereof for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and reference voltage on the second bit line.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a multi-layer hard mask. The multi-layer hard mask comprises a hard masking layer overlying an etch stop layer. The etch stop layer is substantially more selective than the overlying masking layer with respect to an etch employed to remove the bottom electrode diffusion barrier layer. Therefore during an etch of the capacitor stack, an etch of the bottom electrode diffusion barrier layer results in a substantially complete removal of the hard masking layer. However, due to the substantial selectivity (e.g., 10:1 or more) of the etch stop layer with respect to the overlying masking layer, the etch stop layer completely protects the underlying top electrode, thereby preventing exposure thereof.

Abstract: A ferroelectric memory device is disclosed and comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.

Abstract: A ferroelectric memory device is disclosed and comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.

Abstract: An embodiment of the invention is a method of eliminating the surface roughness of the hardmask 4 of a ferroelectric capacitor stacks 2 using a BCl3-based plasma etch.

Abstract: A ferroelectric memory device is disclosed and comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a TiAlON bottom electrode diffusion barrier layer prior to formation of the bottom electrode layer in an FeRAM capacitor stack. Subsequently, when performing the capacitor stack etch, the portion of the TiAlON diffusion barrier layer not covered by the FeRAM capacitor stack is etched substantially anisotropically due to the oxygen within the TiAlON diffusion barrier layer substantially preventing a lateral etching thereof. In the above manner, an undercut of the TiAlON diffusion barrier layer under the FeRAM capacitor stack is prevented. In another aspect of the invention, a method of forming an FeRAM capacitor comprises forming a multi-layer bottom electrode diffusion barrier layer. Such formation comprises forming a TiN layer over the interlayer dielectric layer and the conductive contact and forming a diffusion barrier layer thereover.

Abstract: The present invention forms sidewall diffusion barrier layer(s) that mitigate hydrogen contamination of ferroelectric capacitors. Sidewall diffusion barrier layer(s) of the present invention are formed via a physical vapor deposition process at a low temperature. By so doing, the sidewall diffusion barrier layer(s) are substantially amorphous and provide superior protection against hydrogen diffusion than conventional and/or crystalline sidewall diffusion barrier layers.

Abstract: A method for controlling the crystallographic texture of thin films with anisotropic ferroelectric polarization or permittivity by means of ion bombardment resulting in a texture with higher ferroelectric polarization or permittivity which is normally energetically disfavored.

Abstract: One aspect of the invention relates to a method of manufacturing a semiconductor device in which an alignment mark is formed by a plurality of adjacent filled trenches. A processing tool detects the trenches as though they were a single filled trench of larger dimension. When the trenches are metal filled, the metal is more easily protected from oxidation than when the metal is formed into a single large trench, an effect that is pronounced when the trenches are filled with tungsten. Another aspect of the invention relates to an alignment mark formed by a plurality of tungsten filled trenches. The alignment mark can be used to align the pattern for an FeRAM capacitor stack to underlying tungsten contacts.

Abstract: A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom electrode layer, a protective film is formed on the sidewalls of the capacitor stack structure in order to protect the dielectric material from conductive contaminants associated with a subsequent patterning of the bottom electrode layer.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a TiAlON bottom electrode diffusion barrier layer prior to formation of the bottom electrode layer in an FeRAM capacitor stack. Subsequently, when performing the capacitor stack etch, the portion of the TiAlON diffusion barrier layer not covered by the FeRAM capacitor stack is etched substantially anisotropically due to the oxygen within the TiAlON diffusion barrier layer substantially preventing a lateral etching thereof. In the above manner, an undercut of the TiAlON diffusion barrier layer under the FeRAM capacitor stack is prevented. In another aspect of the invention, a method of forming an FeRAM capacitor comprises forming a multi-layer bottom electrode diffusion barrier layer. Such formation comprises forming a TiN layer over the interlayer dielectric layer and the conductive contact and forming a diffusion barrier layer thereover.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a multi-layer hard mask. The multi-layer hard mask comprises a hard masking layer overlying an etch stop layer. The etch stop layer is substantially more selective than the overlying masking layer with respect to an etch employed to remove the bottom electrode diffusion barrier layer. Therefore during an etch of the capacitor stack, an etch of the bottom electrode diffusion barrier layer results in a substantially complete removal of the hard masking layer. However, due to the substantial selectivity (e.g., 10:1 or more) of the etch stop layer with respect to the overlying masking layer, the etch stop layer completely protects the underlying top electrode, thereby preventing exposure thereof.

Abstract: A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom electrode layer, a protective film is formed on the sidewalls of the capacitor stack structure in order to protect the dielectric material from conductive contaminants associated with a subsequent patterning of the bottom electrode layer.

Abstract: An embodiment of the instant invention is a method of fabricating a ferroelectric capacitor which is situated over a structure, the method comprising the steps of: forming a bottom electrode on the structure (124 of FIG. 1), the bottom electrode having a top surface and sides; forming a capacitor dielectric (126 of FIG. 1) comprised of a ferroelectric material on the bottom electrode, the capacitor dielectric having a top surface and sides; forming a top electrode (128 and 130 of FIG. 1) on the capacitor dielectric, the top electrode having a top surface and sides, the ferroelectric capacitor is comprised of the bottom electrode, the capacitor dielectric, and the top electrode; forming a barrier layer (118 and 120 of FIG.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: A method of fabricating a transistor using silicon on lattice matched insulator. A first monocrystalline silicon layer is provided and a first layer of dielectric is epitaxially deposited over the first silicon layer substantially lattice matched with the first silicon layer and substantially monocrystalline. A first electrically conductive gate electrode is epitaxially formed over the first layer of dielectric substantially lattice matched with the first layer of dielectric. A second layer of dielectric is epitaxially deposited conformally over the first gate electrode and exposed portions of first layer of dielectric substantially lattice matched with the first silicon layer and substantially monocrystalline. A second monocrystalline silicon layer is epitaxially deposited over the second layer of dielectric and a third layer of dielectric is epitaxially deposited over the second silicon layer substantially lattice matched with the first silicon layer and substantially monocrystalline.

Abstract: A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom electrode layer, a protective film is formed on the sidewalls of the capacitor stack structure in order to protect the dielectric material from conductive contaminants associated with a subsequent patterning of the bottom electrode layer.

Abstract: Molecular beam epitaxy (202) with growing layer thickness control (206) by feedback of mass spectrometer (204) signals based on a process model. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes.

Abstract: An apparatus and method for evaluating semiconductor structures and devices are provided. A method for evaluating at least one selected electrical property of a semiconductor device (201) in relation to a selected geometric dimension of the semiconductor device (201). The method further includes forming a plurality of semiconductor devices (201) on a substrate (202), the devices (201) having at least one geometric dimension, measuring the at least one electrical property of at least one of the semiconductor devices (201) using a scanning probe microscopy based technique, and determining a relationship between the measured electrical property and the selected geometric dimension of the semiconductor device (201). The method further includes evaluating at least one semiconductor fabrication process based upon the determined relationship.