Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: A method for simultaneously producing areas of paraelectric states and areas of ferroelectric states on a single thin film layer, thereby reducing the number of processing steps required to produce integrated chips containing both standard capacitors and non-volatile memory devices from the number of steps needed using the conventional approach. A device containing both ferroelectric capacitors and non-ferroelectric capacitors using a single thin film as the dielectric.

Abstract: An apparatus and method for evaluating semiconductor structures and devices are provided. The present invention provides a method for evaluating at least one selected electrical property of a semiconductor device (201) in relation to a selected geometric dimension of the semiconductor device (201). The method further includes forming a plurality of semiconductor devices (201) on a substrate (202), the devices (201) having at least one geometric dimension, measuring the at least one electrical property of at least one of the semiconductor devices (201) using a scanning probe microscopy based technique, and determining a relationship between the measured electrical property and the selected geometric dimension of the semiconductor device (201). The method further includes evaluating at least one semiconductor fabrication process based upon the determined relationship.

Abstract: A ferroelectric structure on an integrated circuit and methods of making and using the same are disclosed, which may be used, for instance, in a high-speed, non-volatile, non-destructive readout random-access memory device. Generally, the ferroelectric structure combines a thin film ferroelectric variable resistor and a substrate (e.g. silicon) transistor, using a semiconducting film which is common to both. A field effect transistor 26 integrated into substrate 30 has a gate oxide 36 and a semiconducting gate electrode 38 with electrical connections at a first end 44 and a second end 46. Overlying gate electrode 38 is a ferroelectric thin film 40 and a conductive electrode 42. The polarization of ferroelectric thin film 40 is set by applying an appropriate voltage between gate electrode 38 and conductive electrode 42.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: A ferroelectric structure on an integrated circuit is disclosed, which may be used, for instance, in a high-speed, non-volatile, non-destructive readout random-access memory device. Generally, the ferroelectric structure combines a thin film ferroelectric variable resistor and a substrate (e.g. silicon) transistor, using a semiconducting film which is common to both. A field effect transistor 26 integrated into substrate 30 has a gate oxide 36 and a semiconducting gate electrode 38 with electrical connections at a first end 44 and a second end 46. Overlying gate electrode 38 is a ferroelectric thin film 40 and a conductive electrode 42. The polarization of ferroelectric thin film 40 is set by applying an appropriate voltage between gate electrode 38 and conductive electrode 42.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: A method for etching a platinum surface 200. The method includes the step of forming a hardmask 202 including titanium, aluminum, and nitrogen on the platinum surface. The hardmask covers portions of the platinum surface. The method further includes removing platinum from uncovered portions of the surface with a plasma including a nitrogen-bearing species. The etch chemistry may also comprise an oxygen-bearing species.

Abstract: The present invention is a method related to the deposition of a metallization layer in a trench in a semiconductor substrate. The focus of the invention is to sequentially perform heated deposition and etch unit processes to provide a good conformal film of metal on the inner surfaces of a via or trench. The deposition and etch steps can also be performed simultaneously.

Abstract: Apparatus for optical communications (10, 20, 30, 60 90) includes an optically switched resonant tunneling device (12, 22, 42, 62, 92) being exposed to an input light. The optically switched resonant tunneling device (12, 22, 42, 62, 92) generates a first and second voltage levels in response to the intensity level of the input light. A lasing device (16, 28, 46, 68, 74, 100) is coupled to the optically switched resonant tunneling device (12, 22, 42, 62, 92). The lasing device (16, 28, 46, 68, 74, 100) generates and modulates an output light in response to the first and second voltage levels.

Abstract: Molecular beam epitaxy (202) with growing layer thickness control (206) by feedback of mass spectrometer (204) signals based on a process model. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes.

Abstract: Apparatus for optical communications (10, 110, 210) includes a low-temperature grown photoconductor (12, 140, 220) coupled to at least one resonant tunneling device (14, 120, 130, 230, 240). When exposed to an input light, low-temperature grown photoconductor (10, 110, 210) absorbs photons, which decreases the resistivity, and thus the resistance of the photoconductor. This decrease in resistance causes a decrease in the voltage drop across photoconductor (12, 140, 220), which causes a corresponding increase in the voltage drop across resonant tunneling device (14, 120, 130, 230, 140).

Abstract: A hot-electron transistor (10) is formed on substrate (12) having an outer surface. The present transistor includes subcollector layer (14) comprising Indium Gallium Arsenide formed outwardly from the outer surface of substrate (12). Collector barrier layer (18) comprising Indium Aluminum Gallium Arsenide is outwardly formed from subcollector layer (14), and collector barrier layer (18) minimizes leakage current in transistor (10). Outwardly from collector barrier layer (18) is formed base layer (20) comprising Indium Gallium Arsenide. Tunnel injector layer (21) comprising Aluminum Arsenide for ballistically transporting electrons in transistor (10) is outwardly formed from base layer (20), and emitter layer (24) comprising Indium Aluminum Arsenide is outwardly formed from tunnel injector layer (21).