Patents by Inventor Thomas Gehrke

Thomas Gehrke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8105921
    Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: January 31, 2012
    Assignee: International Rectifier Corporation
    Inventors: T. Warren Weeks, Jr., Edwin Lanier Piner, Thomas Gehrke, Kevin J. Linthicum
  • Publication number: 20120012812
    Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and a plurality of hemispherical grained silicon (“HSG”) structures on the substrate surface of the substrate material. The solid state lighting device also includes a semiconductor material on the substrate material, at least a portion of which is between the plurality of HSG structures.
    Type: Application
    Filed: July 16, 2010
    Publication date: January 19, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Cem Basceri, Thomas Gehrke
  • Publication number: 20120013273
    Abstract: Solid state lighting devices that can produce white light without a phosphor are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The active region includes a first sub-region having a first center wavelength and a second sub-region having a second center wavelength different from the first center wavelength.
    Type: Application
    Filed: July 16, 2010
    Publication date: January 19, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Zaiyuan Ren, Thomas Gehrke
  • Publication number: 20110233581
    Abstract: Solid state lighting (“SSL”) devices with cellular arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode includes a semiconductor material having a first surface and a second surface opposite the first surface. The semiconductor material has an aperture extending into the semiconductor material from the first surface. The light emitting diode also includes an active region in direct contact with the semiconductor material, and at least a portion of the active region is in the aperture of the semiconductor material.
    Type: Application
    Filed: March 25, 2010
    Publication date: September 29, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Scott Sills, Lifang Xu, Scott Schellhammer, Thomas Gehrke, Zaiyuan Ren, Anton De Villiers
  • Publication number: 20110217800
    Abstract: A method and system for manufacturing a light conversion structure for a light emitting diode (LED) is disclosed. The method includes forming a transparent, thermally insulating cover over an LED chip. The method also includes dispensing a conversion material onto the cover to form a conversion coating on the cover, and encapsulating the LED, the silicone cover, and the conversion coating within an encapsulant. Additional covers and conversion coatings can be added.
    Type: Application
    Filed: March 2, 2010
    Publication date: September 8, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Charles M. Watkins, Kevin Tetz, Thomas Gehrke
  • Publication number: 20110210353
    Abstract: Light emitting diodes (“LEDs”) with N-polarity and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a light emitting diode on a substrate having a substrate material includes forming a nitrogen-rich environment at least proximate a surface of the substrate without forming a nitrodizing product of the substrate material on the surface of the substrate. The method also includes forming an LED structure with a nitrogen polarity on the surface of the substrate with a nitrogen-rich environment.
    Type: Application
    Filed: February 26, 2010
    Publication date: September 1, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Zaiyuan Ren, Thomas Gehrke
  • Publication number: 20110193115
    Abstract: Light emitting diodes and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode (LED) includes a substrate, a semiconductor material carried by the substrate, and an active region proximate to the semiconductor material. The semiconductor material has a first surface proximate to the substrate and a second surface opposite the first surface. The second surface of the semiconductor material is generally non-planar, and the active region generally conforms to the non-planar second surface of the semiconductor material.
    Type: Application
    Filed: February 10, 2010
    Publication date: August 11, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Scott Schellhammer, Scott Sills, Lifang Xu, Thomas Gehrke, Zaiyuan Ren, Anton De Villiers
  • Publication number: 20090104758
    Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.
    Type: Application
    Filed: December 24, 2008
    Publication date: April 23, 2009
    Applicant: Nitronex Corporation
    Inventors: T. Warren Weeks, JR., Edwin L. Piner, Thomas Gehrke, Kevin J. Linthicum
  • Patent number: 7485512
    Abstract: A method of compensating resistivity of a near-surface region of a substrate includes epitaxially growing a buffer layer on the substrate, wherein the buffer is grown as having a dopant concentration as dependent on resistivity and conductivity of the substrate, so as to deplete residual or excess charge within the near-surface region of the substrate. The dopant profile of the buffer layer be smoothly graded, or may consist of sub-layers of different dopant concentration, to also provide a highly resistive upper portion of the buffer layer ideal for subsequent device growth. Also, the buffer layer may be doped with carbon, and aluminum may be used to getter the carbon during epitaxial growth.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: February 3, 2009
    Assignee: Cree, Inc.
    Inventors: Christopher Harris, Thomas Gehrke, T. Warren Weeks, Jr., Cem Basceri, Elif Berkman
  • Patent number: 7378684
    Abstract: An underlying gallium nitride layer on a silicon carbide substrate is masked with a mask that includes an array of openings therein, and the underlying gallium nitride layer is etched through the array of openings to define posts in the underlying gallium nitride layer and trenches therebetween. The posts each include a sidewall and a top having the mask thereon. The sidewalls of the posts are laterally grown into the trenches to thereby form a gallium nitride semiconductor layer. During this lateral growth, the mask prevents nucleation and vertical growth from the tops of the posts. Accordingly, growth proceeds laterally into the trenches, suspended from the sidewalls of the posts. The sidewalls of the posts may be laterally grown into the trenches until the laterally grown sidewalls coalesce in the trenches to thereby form a gallium nitride semiconductor layer.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: May 27, 2008
    Assignee: North Carolina State University
    Inventors: Kevin J. Linthicum, Thomas Gehrke, Darren B. Thomson, Eric P. Carlson, Pradeep Rajagopal, Robert F. Davis
  • Patent number: 7364988
    Abstract: A method of manufacturing a heterojunction device includes forming a first layer of p-type aluminum gallium nitride; forming a second layer of undoped gallium nitride on the first layer; and forming a third layer of aluminum gallium nitride on the second layer, to provide an electron gas between the second and third layers. A heterojunction between the first and second layers injects positive charge into the second layer to compensate and/or neutralize negative charge within the electron gas.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: April 29, 2008
    Assignee: Cree, Inc.
    Inventors: Christopher Harris, Thomas Gehrke, T. Warren Weeks, Jr., Cem Basceri
  • Patent number: 7326971
    Abstract: A heterojunction device includes a first layer of p-type aluminum gallium nitride; a second layer of undoped gallium nitride on the first layer; a third layer of aluminum gallium nitride on the second layer; and an electron gas between the second and third layers. A heterojunction between the first and second layers injects positive charge into the second layer to compensate and/or neutralize negative charge within the electron gas.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: February 5, 2008
    Assignee: Cree, Inc.
    Inventors: Christopher Harris, Thomas Gehrke, T. Warren Weeks, Jr., Cem Basceri
  • Publication number: 20070200116
    Abstract: A dimpled substrate and method of making including a substrate of high thermal conductivity having a first main surface and a second main surface opposite the first main surface. Active epitaxial layers are formed on the first main surface of the substrate. Dimples are formed as extending from the second main surface into the substrate toward the first main surface. An electrical contact of low resistance material is disposed on the second main surface and within the dimples. A back contact of low resistance and low loss is thus provided while maintaining the substrate as an effective heat sink.
    Type: Application
    Filed: January 10, 2007
    Publication date: August 30, 2007
    Inventors: Christopher Harris, Cem Basceri, Thomas Gehrke, Cengiz Balkas
  • Patent number: 7217641
    Abstract: More specifically, gallium nitride semiconductor layers may be fabricated by etching an underlying gallium nitride layer on a sapphire substrate, to define at least one post in the underlying gallium nitride layer and at least one trench in the underlying gallium nitride layer. The at least one post includes a gallium nitride top and a gallium nitride sidewall. The at least one trench includes a trench floor. The gallium nitride sidewalls are laterally grown into the at least one trench, to thereby form a gallium nitride semiconductor layer. However, prior to performing the laterally growing step, the sapphire substrate and/or the underlying gallium nitride layer is treated to prevent growth of gallium nitride from the trench floor from interfering with the lateral growth of the gallium nitride sidewalls of the at least one post into the at least one trench.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: May 15, 2007
    Assignee: North Carolina State University
    Inventors: Thomas Gehrke, Kevin J. Linthicum, Robert F. Davis
  • Patent number: 7195993
    Abstract: A gallium nitride layer is laterally grown into a trench in the gallium nitride layer, to thereby form a lateral gallium nitride semiconductor layer. At least one microelectronic device may then be formed in the lateral gallium nitride semiconductor layer. Dislocation defects do not significantly propagate laterally into the lateral gallium nitride semiconductor layer, so that the lateral gallium nitride semiconductor layer is relatively defect free.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: March 27, 2007
    Assignee: North Carolina State University
    Inventors: Tsvetanka Zheleva, Darren B. Thomson, Scott A. Smith, Kevin J. Linthicum, Thomas Gehrke, Robert F. Davis
  • Publication number: 20060281238
    Abstract: A method of compensating resistivity of a near-surface region of a substrate includes epitaxially growing a buffer layer on the substrate, wherein the buffer is grown as having a dopant concentration as dependent on resistivity and conductivity of the substrate, so as to deplete residual or excess charge within the near-surface region of the substrate. The dopant profile of the buffer layer be smoothly graded, or may consist of sub-layers of different dopant concentration, to also provide a highly resistive upper portion of the buffer layer ideal for subsequent device growth. Also, the buffer layer may be doped with carbon, and aluminum may be used to getter the carbon during epitaxial growth.
    Type: Application
    Filed: June 26, 2006
    Publication date: December 14, 2006
    Inventors: Christopher Harris, Thomas Gehrke, T. Weeks, Cem Basceri, Elif Berkman
  • Publication number: 20060278892
    Abstract: A heterojunction device includes a first layer of p-type aluminum gallium nitride; a second layer of undoped gallium nitride on the first layer; a third layer of aluminum gallium nitride on the second layer; and an electron gas between the second and third layers. A heterojunction between the first and second layers injects positive charge into the second layer to compensate and/or neutralize negative charge within the electron gas.
    Type: Application
    Filed: June 8, 2005
    Publication date: December 14, 2006
    Inventors: Christopher Harris, Thomas Gehrke, T. Weeks, Cem Basceri
  • Publication number: 20060281284
    Abstract: A method of manufacturing a heterojunction device includes forming a first layer of p-type aluminum gallium nitride; forming a second layer of undoped gallium nitride on the first layer; and forming a third layer of aluminum gallium nitride on the second layer, to provide an electron gas between the second and third layers. A heterojunction between the first and second layers injects positive charge into the second layer to compensate and/or neutralize negative charge within the electron gas.
    Type: Application
    Filed: June 8, 2005
    Publication date: December 14, 2006
    Inventors: Christopher Harris, Thomas Gehrke, T. Weeks, Cem Basceri
  • Patent number: 7095062
    Abstract: A substrate includes non-gallium nitride posts that define trenches therebetween, wherein the non-gallium nitride posts include non-gallium nitride sidewalls and non-gallium nitride tops and the trenches include non-gallium floors. Gallium nitride is grown on the non-gallium nitride posts, including on the non-gallium nitride tops. Preferably, gallium nitride pyramids are grown on the non-gallium nitride tops and gallium nitride then is grown on the gallium nitride pyramids. The gallium nitride pyramids preferably are grown at a first temperature and the gallium nitride preferably is grown on the pyramids at a second temperature that is higher than the first temperature. The first temperature preferably is about 1000° C. or less and the second temperature preferably is about 1100° C. or more. However, other than temperature, the same processing conditions preferably are used for both growth steps. The grown gallium nitride on the pyramids preferably coalesces to form a continuous gallium nitride layer.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: August 22, 2006
    Assignee: North Carolina State University
    Inventors: Kevin J. Linthicum, Thomas Gehrke, Robert F. Davis
  • Patent number: 6956250
    Abstract: The invention includes providing gallium nitride materials including thermally conductive regions and methods to form such materials. The gallium nitride materials may be used to form semiconductor devices. The thermally conductive regions may include heat spreading layers and heat sinks. Heat spreading layers distribute beat generated during device operation over relatively large areas to prevent excessive localized heating. Heat sinks typically are formed at either the backside or topside of the device and facilitate heat dissipation to the environment. It may be preferable for devices to include a heat spreading layer which is connected to a heat sink at the backside of the device. A variety of semiconductor devices may utilize features of the invention including devices on silicon substrates and devices which generate large amounts of heat such as power transistors.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: October 18, 2005
    Assignee: Nitronex Corporation
    Inventors: Ricardo Borges, Kevin J. Linthicum, T. Warren Weeks, Thomas Gehrke