Abstract: A method for processing an input composite signal includes tracking a signal component of the input composite signal according to a frequency of a pilot signal to generate a locked signal, detecting an amplitude of the signal component to generate a detecting result, and generating a reproduced pilot signal according to the detecting result and the locked signal. A frequency and a phase of the locked signal are substantially identical to the frequency and a phase of the pilot signal.

Abstract: The present invention is directed to a recoverable Ethernet receiver. A joint decision feedback equalizer (DFE) and Trellis decoder is configured to decode a receiving signal to result in a received symbol, and configured to generate a check-idle value which is used to indicate an idle mode. A physical coding sublayer (PCS) block is configured to generate a seed value and a polarity characterization according to the received symbol, with the joint DFE and Trellis decoder generating the check-idle value according to the seed value and the polarity characterization.

Abstract: The invention discloses a digital IF demodulator for processing a digital IF signal converted from a radio frequency (RF) signal, including an NCO, a down conversion circuit, a PIF carrier recovery circuit and a video baseband demodulator. The NCO outputs a sine value and a cosine value. The down conversion circuit outputs a first zero IF signal including a first real part signal and a first imaginary part signal, according to the digital IF signal, the sine value and the cosine value. The PIF carrier recovery circuit outputs a loop error signal for the NCO and a second zero IF signal, according to the first zero IF signal and a video synchronization signal. The video baseband demodulator generates a composite video signal according to the second zero IF signal.

Abstract: A broadcast receiver includes a tuner circuit and a demodulator circuit. The tuner circuit tunes a radio frequency (RF) signal to output an intermediate frequency (IF) signal. The demodulator circuit demodulates the IF signal from the tuner circuit and outputs a command signal based on the quality of the IF signal, for changing a take over point (TOP) value, preset in the tuner circuit, at which one amplitude gain control (AGC) stopping and another taking over. A method for regulating a broadcast receiver is also disclosed herein.

Abstract: An apparatus for generating sine/cosine values of an input phase is disclosed. The apparatus includes a phase projector, an LUT-arithmetic unit, a temp sine/cosine generator and a sine/cosine value generator. The phase projector maps the input phase angle into an octant phase and determines an octant index indicating which octant the input phase angle actually locates and a flag indicating whether or not the input phase happens to be pi/4, 3*pi/4, 5*pi/4 or 7*pi/4. The LUT-arithmetic unit receives the octant phase for provision of its corresponding sine/cosine values. The temp sine/cosine generator receives the corresponding sine/cosine values of the octant phase for provision of temp sine/cosine values based on the flag. The sine/cosine value generator selectively swaps and inverts the temp sine/cosine values as the sine/cosine values of the input phase based on a swap index derived from the octant index.

Abstract: The present invention is directed to joint decision feedback equalizer (DFE) and Trellis decoder adaptable to an Ethernet transceiver. A Trellis coded modulation (TCM) decoder includes a one-dimensional branch metric unit (1D-BMU) configured to calculate 1D branch metrics; a four-dimensional branch metric unit (4D-BMU) configured to combine the 1D branch metrics to generate 4D branch metrics; an add-compare-select unit (ACSU) configured to perform add, compare and select (ACS) operations on the 4D branch metrics for each state to obtain path metrics; and a survivor memory unit (SMU) configured to store and keep track of symbols. A decision feedback unit (DFU) is coupled to receive the symbols from the SMU in order to estimate inter-symbol interference (ISI) quantity, which is then fed back to the 1D-BMU.

Abstract: An adaptive Ethernet transceiver is disclosed. A joint decision feedback equalizer (DFE) and Trellis decoder is configured to decode a receiving signal. A decoder control unit is configured to adaptively disable a portion of the joint DFE and Trellis decoder in a non-specified link speed mode.

Abstract: The present invention is directed to a recoverable Ethernet receiver. A joint decision feedback equalizer (DFE) and Trellis decoder is configured to decode a receiving signal to result in a received symbol, and configured to generate a check-idle value which is used to indicate an idle mode. A physical coding sublayer (PCS) block is configured to generate a seed value and a polarity characterization according to the received symbol, with the joint DFE and Trellis decoder generating the check-idle value according to the seed value and the polarity characterization.

Abstract: A decoder and related method adaptively generate a clock window. A falling edge of a horizontal synchronization signal is detected, and the time difference between an actual frame code and a predefined frame code is determined. The beginning and the end of the clock window are then adaptively determined based on the falling edge and the time difference, such that symbol timing recovery through received clock run-in signals may be performed within the generated clock window.

Abstract: A receiver with capability of correcting error is disclosed. A soft slicer generates quantized data and associated soft data. A decoder with error recovery generates decoded quantized data and a soft sequence, and is capable of correcting one bit of the quantized data. A serial-to-parallel (S/P) converter with code corrector generates parallel data, and is capable of correcting two bits of de-scrambled data bits.

Abstract: A method and system of receiving data with enhanced partial matching is disclosed. A received word is compared with the frame code to determine mismatch bit(s). Subsequently, a determination is made whether the mismatch bit(s) are at positions of defined critical bits. If the mismatch bit(s) are not critical, the received word is then affirmed.

Abstract: A video horizontal synchronizer outputting a line timing signal and an indicating flag of a received video signal for use in a video signal post-processing unit, including a filter outputting a wide bandwidth filtered and a narrow bandwidth filtered signals of the received video signal, a dynamic slicer threshold generator generating a slicer threshold, a timing recovery circuit generating a phase error and the line timing signal, a phase error statistics circuit averaging the phase error to generate a average phase error, a HSYNC checker generating a matching flag indicating whether a periodic pattern appears in the narrow bandwidth filtered signal according to the line timing signal, and a finite state machine controlling the dynamic slicer threshold generator, the timing recovery circuit, the phase error statistics circuit and the HSYNC checker and generating an indicating flag when the average phase error is small enough and the matching flag is confirmed.

Abstract: A sound-IF demodulator including a first demodulating unit and a second demodulating unit and a sound-IF detecting method thereof are provided. A sound de-matrix unit is adapted to generate a driving signal by de-matrixing outputs of the sound-IF demodulator. The first demodulating unit generates a first demodulated signal to the sound de-matrix unit by demodulating the first carrier signal. The second demodulating unit detects the signal quality of the sound signal and generates a second demodulated signal to the sound de-matrix unit and/or the first demodulating unit by demodulating the second carrier signal. When the second demodulating unit is idle, the second demodulating unit is programmed to select a corresponding standard among a plurality of predetermined standards for the sound signal according to the signal quality of the sound signal, so that the sound-IF demodulator is programmed to demodulate the sound signal in the corresponding standard.

Abstract: A transceiver having HEAC and Ethernet connections is disclosed. An active hybrid & common-mode bias (AHCB) unit facilitates the transmission of differential transmission signals and the reception of first differential reception signals. An Ethernet line gate controllably configures the pairing among first and second differential Ethernet signals, the differential transmission signals and second differential reception signals. An Ethernet physical-layer (PHY) transceiving unit receives both or one of the first and second differential reception signals and the differential transmission signals, followed by processing the reception signals at a physical layer.

Abstract: A digital demodulator adapted in a receiver and a digital demodulation method are provided. The digital demodulator includes: a phase splitter, a complex multiplier, an AFC, a limiter, a phase detector, a re-tracker, a post-multiplier and an oscillator. The phase splitter generates a complex signal from the input signal. The complex multiplier multiplies the complex signal by both first and second phase signals to generate first and second base band signals. The AFC generates a first output signal. The limiter generates a trend signal and the re-tracker generates a tuning signal from the first output signal. The phase detector multiplies the trend and second base signal and adjusts the multiplied signal based on the tuning signal. The oscillator generates the first and second phase signals according to the output of the phase detector. The post-multiplier multiplies the trend signal by the first and second base band signals for output.

Abstract: A method for determining a sound standard for an input sound signal includes the following steps. Firstly, the input sound signal is filtered to obtain a first filtered signal corresponding to a first frequency and a second filtered signal corresponding to a second frequency. Next, the first filtered signal is frequency-demodulated to obtain a first demodulated filtered signal, and whether the input sound signal contains a FM analog component corresponding to the first frequency is determined accordingly. Next, the second filtered signal is decoded according to a digital sound standard to obtain a bit stream. Then, the bit steam is interpreted according to the digital sound standard, and whether the input sound contains a digital component corresponding to the digital sound standard is determined accordingly. Then, whether the input sound signal matches one of known sound standards is determined based on the determined results above.

Abstract: A receiver with capability of correcting error is disclosed. A soft slicer generates quantized data and associated soft data. A decoder with error recovery generates decoded quantized data and a soft sequence, and is capable of correcting one bit of the quantized data. A serial-to-parallel (S/P) converter with code corrector generates parallel data, and is capable of correcting two bits of de-scrambled data bits.

Abstract: A system and method for generating test patterns of baseline wander, such as worst-case test patterns commonly referred to as killer packets. The number of steps required to cycle an output of a multi-level encoder in order to arrive at an anticipated level is determined. A test packet generator then generates the test patterns according to the determined steps and the state of a scrambler.

Abstract: A system and method for generating test patterns of baseline wander, such as worst-case test patterns commonly referred to as killer packets. The number of steps required to cycle an output of a multi-level encoder in order to arrive at an anticipated level is determined. A test packet generator then generates the test patterns according to the determined steps and the state of a scrambler.

Abstract: A decimator is used to process a multi-channel audio signal, and includes a memory, a controller and a processing unit. The processing unit is used to decimate each input audio component of a multi-channel audio signal to generate corresponding multi-channel operational data. The controller is used to control read and write actions for each audio component of the multi-channel audio signal and the multi-channel operational data into or from the memory. The memory provides a digital signal process for decimation together with the processing unit. The input of the multi-channel audio and the output of the multi-channel operational data are performed through time division. Compared with conventional decimator circuits, the decimator circuit of the present invention reduces the cost and the power consumption of the hardware circuitry.