Abstract: A method for frequency compensation includes the following steps: detecting and checking if a desired frequency falls within a first detectable frequency range delimited by an initial frequency and a first specific frequency; and when the desired frequency exceeds the first detectable frequency range, utilizing a first frequency compensation step with a step size greater than a size of the first detectable frequency range for shifting the initial frequency to a first adjusted frequency beyond the first specific frequency in a first direction.

Abstract: A decoder and related method adaptively generate a clock window. A falling edge of a horizontal synchronization signal is detected, and the time difference between an actual frame code and a predefined frame code is determined. The beginning and the end of the clock window are then adaptively determined based on the falling edge and the time difference, such that symbol timing recovery through received clock run-in signals may be performed within the generated clock window.

Abstract: A method and system of receiving data with enhanced partial matching is disclosed. A received word is compared with the frame code to determine mismatch bit(s). Subsequently, a determination is made whether the mismatch bit(s) are at positions of defined critical bits. If the mismatch bit(s) are not critical, the received word is then affirmed.

Abstract: A noise reduction system is used in a BTSC system to reduce noise of an audio signal. The noise reduction system has an audio spectral compressing unit that has a filter and a memory in the approach of the digital processing. The filter is arranged to filter an input signal according to a transfer function, a variable d, and several parameters b0/a0, a0/b0, b1/b0 and a1/a0. The memory is arranged to store the parameters.

Abstract: A method for receiving a station signal is provided. First, a radio frequency signal is received and converted to a first IF signal. Next, the first IF signal is demodulated to a baseband signal and a demodulation signal is obtained, the demodulation signal being a result of differentiating a phase of the baseband signal. Then a determination as to whether a DC level of the demodulation signal has an S-curve characteristic at a specific frequency is made according to the demodulation signal. If so, the specific frequency is determined as a first station frequency, a first station signal is obtained from the radio frequency signal according to the first station frequency.

Abstract: A video horizontal synchronizer outputting a line timing signal and an indicating flag of a received video signal for use in a video signal post-processing unit, including a filter outputting a wide bandwidth filtered and a narrow bandwidth filtered signals of the received video signal, a dynamic slicer threshold generator generating a slicer threshold, a timing recovery circuit generating a phase error and the line timing signal, a phase error statistics circuit averaging the phase error to generate a average phase error, a HSYNC checker generating a matching flag indicating whether a periodic pattern appears in the narrow bandwidth filtered signal according to the line timing signal, and a finite state machine controlling the dynamic slicer threshold generator, the timing recovery circuit, the phase error statistics circuit and the HSYNC checker and generating an indicating flag when the average phase error is small enough and the matching flag is confirmed.

Abstract: A Radio Data System (RDS) decoder circuit determines a subcarrier frequency utilizing only a 57 kHz RDS signal of an FM broadcast signal. The RDS decoder includes a zero-intermediate frequency (zero-IF) FM demodulator, a first mixer, a low-pass filter (LPF) unit, a shaping filter unit, a carrier recovery circuit, a digitally controlled oscillator (DCO), a symbol timing recovery circuit, an integrate and dump circuit, a slicer 280, and a differential decoder. The carrier recovery circuit includes a phase error detector and a digital loop filter (DLF). The symbol timing recovery circuit includes a zero-crossing detector, a phase detector and loop filter unit, and a counter.

Abstract: A sound-IF demodulator including a first demodulating unit and a second demodulating unit and a sound-IF detecting method thereof are provided. A sound de-matrix unit is adapted to generate a driving signal by de-matrixing outputs of the sound-IF demodulator. The first demodulating unit generates a first demodulated signal to the sound de-matrix unit by demodulating the first carrier signal. The second demodulating unit detects the signal quality of the sound signal and generates a second demodulated signal to the sound de-matrix unit and/or the first demodulating unit by demodulating the second carrier signal. When the second demodulating unit is idle, the second demodulating unit is programmed to select a corresponding standard among a plurality of predetermined standards for the sound signal according to the signal quality of the sound signal, so that the sound-IF demodulator is programmed to demodulate the sound signal in the corresponding standard.

Abstract: A system for tracking a tone (carrier) within a frequency range is provided. The carrier tracking system includes a complex frequency down-converter, a waveform generator, a coordinate converter, and a control circuit. The frequency down-converter generates a Cartesian signal by mixing an input signal and sine and cosine signals. The waveform generator generates the sine and cosine signals based on a frequency bias signal. The coordinate converter converts the Cartesian signal into a polar signal having a norm signal and a phase signal. The control circuit selects a candidate frequency within a predetermined frequency range based on the norm signal and a estimated frequency deviation corresponding to the candidate frequency based on the phase signal, and generates the frequency bias signal based on the candidate frequency, the estimated frequency deviation and a loop error determined by the phase signal.

Abstract: A method and system of receiving data with enhanced error correction is disclosed. One or more reliability bits associated with each received data bit are generated, for example, by a soft-decision slicer. Subsequently, one or more errors of the data bits may be corrected according to the associated reliability bit(s).

Abstract: The invention discloses a digital IF demodulator for processing a digital IF signal converted from a radio frequency (RF) signal, including an NCO, a down conversion circuit, a PIF carrier recovery circuit and a video baseband demodulator. The NCO outputs a sine value and a cosine value. The down conversion circuit outputs a first zero IF signal including a first real part signal and a first imaginary part signal, according to the digital IF signal, the sine value and the cosine value. The PIF carrier recovery circuit outputs a loop error signal for the NCO and a second zero IF signal, according to the first zero IF signal and a video synchronization signal. The video baseband demodulator generates a composite video signal according to the second zero IF signal.

Abstract: A broadcast receiver includes a tuner circuit and a demodulator circuit. The tuner circuit tunes a radio frequency (RF) signal to output an intermediate frequency (IF) signal. The demodulator circuit demodulates the IF signal from the tuner circuit and outputs a command signal based on the quality of the IF signal, for changing a take over point (TOP) value, preset in the tuner circuit, at which one amplitude gain control (AGC) stopping and another taking over. A method for regulating a broadcast receiver is also disclosed herein.

Abstract: An apparatus for generating sine/cosine values of an input phase is disclosed. The apparatus includes a phase projector, an LUT-arithmetic unit, a temp sine/cosine generator and a sine/cosine value generator. The phase projector maps the input phase angle into an octant phase and determines an octant index indicating which octant the input phase angle actually locates and a flag indicating whether or not the input phase happens to be pi/4, 3*pi/4, 5*pi/4 or 7*pi/4. The LUT-arithmetic unit receives the octant phase for provision of its corresponding sine/cosine values. The temp sine/cosine generator receives the corresponding sine/cosine values of the octant phase for provision of temp sine/cosine values based on the flag. The sine/cosine value generator selectively swaps and inverts the temp sine/cosine values as the sine/cosine values of the input phase based on a swap index derived from the octant index.

Abstract: A NICAM system includes a NICAM deframer, a FIFO buffer and a symbol rate conversion (SRC) unit. The NICAM deframer obtains multiple deinterleaved symbols according to a strobe signal and a data signal in each timing and expands the deinterleaved symbols to corresponding multiple pulse code modulation (PCM) symbols. The FIFO buffer temporarily stores the symbols and outputs the PCM symbols at a local timing, rate. The SRC unit determines whether a SRC function is enabled according to the statuses of the symbols in the FIFO buffer every a constant time interval. When the SRC function is enabled, the SRC unit interpolates the PCM symbols to obtain multiple new PCM symbols and outputs the new PCM symbols at the local timing rate.

Abstract: A digital demodulator adapted in a receiver and a digital demodulation method are provided. The digital demodulator comprises: a phase splitter, a complex multiplier, an AFC, a limiter, a phase detector, a re-tracker, a post-multiplier and an oscillator. The phase splitter generates a complex signal from the input signal. The complex multiplier multiplies the complex signal by both first and second phase signals to generate first and second base band signals. The AFC generates a first output signal. The limiter generates a trend signal and the re-tracker generates a tuning signal from the first output signal. The phase detector multiplies the trend and second base signal and adjusts the multiplied signal based on the tuning signal. The oscillator generates the first and second phase signals according to the output of the phase detector. The post-multiplier multiplies the trend signal by the first and second base band signals for output.

Abstract: A transmission convergence sublayer circuit is coupled between a buffer and a deframer. The deframer submits a data stream enable signal and data bytes to the circuit. The data stream enable signal enables the circuit so that multiple groups of byte data belonging to a data cell are received and temporarily stored inside a byte-wise data pipeline. A header cyclic redundancy checker also receives the byte data and then conducts a header search. An idle cell identifier is used to determine if the data cell is a non-idle cell. When the header is found and determined to be a non-idle cell, a descrambler retrieves payload data of data cell from the byte-wise data pipeline and conducts a descrambling operation after obtaining a quantity of data equal to a double word. Ultimately, the double word data is output to the buffer with minimum delay.

Abstract: A method for processing an input composite signal includes tracking a signal component of the input composite signal according to a frequency of a pilot signal to generate a locked signal, detecting an amplitude of the signal component to generate a detecting result, and generating a reproduced pilot signal according to the detecting result and the locked signal. A frequency and a phase of the locked signal are substantially identical to the frequency and a phase of the pilot signal.

Abstract: A method for determining a sound standard for an input sound signal includes the following steps. Firstly, the input sound signal is filtered to obtain a first filtered signal corresponding to a first frequency and a second filtered signal corresponding to a second frequency. Next, the first filtered signal is frequency-demodulated to obtain a first demodulated filtered signal, and whether the input sound signal contains a FM analog component corresponding to the first frequency is determined accordingly. Next, the second filtered signal is decoded according to a digital sound standard to obtain a bit stream. Then, the bit steam is interpreted according to the digital sound standard, and whether the input sound contains a digital component corresponding to the digital sound standard is determined accordingly. Then, whether the input sound signal matches one of known sound standards is determined based on the determined results above.

Abstract: A Radio Data System (RDS) decoder circuit determines a subcarrier frequency utilizing only a 57 kHz RDS signal of an FM broadcast signal. The RDS decoder includes a zero-intermediate frequency (zero-IF) FM demodulator, a first mixer, a low-pass filter (LPF) unit, a shaping filter unit, a carrier recovery circuit, a digitally controlled oscillator (DCO), a symbol timing recovery circuit, an integrate and dump circuit, a slicer 280, and a differential decoder. The carrier recovery circuit includes a phase error detector and a digital loop filter (DLF). The symbol timing recovery circuit includes a zero-crossing detector, a phase detector and loop filter unit, and a counter.

Abstract: A NICAM system includes a NICAM deframer, a FIFO buffer and a symbol rate conversion (SRC) unit. The NICAM deframer obtains multiple deinterleaved symbols according to a strobe signal and a data signal in each timing and expands the deinterleaved symbols to corresponding multiple pulse code modulation (PCM) symbols. The FIFO buffer temporarily stores the symbols and outputs the PCM symbols at a local timing, rate. The SRC unit determines whether a SRC function is enabled according to the statuses of the symbols in the FIFO buffer every a constant time interval. When the SRC function is enabled, the SRC unit interpolates the PCM symbols to obtain multiple new PCM symbols and outputs the new PCM symbols at the local timing rate.