Patents by Inventor Tien-Ju Tsai

Tien-Ju Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080303958
    Abstract: A method for receiving a station signal is provided. First, a radio frequency signal is received and converted to a first IF signal. Next, the first IF signal is demodulated to a demodulation signal and a first parameter is obtained within, the first parameter being a DC level of the demodulation signal. Then a determination as to whether the demodulation signal has an S-curve characteristic is made according to the first parameter. If so, the scanning frequency is determined as a first station frequency, a first station signal is located from the radio frequency signal according to the first station frequency and is received.
    Type: Application
    Filed: June 8, 2007
    Publication date: December 11, 2008
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Tien-Ju Tsai, Shu-Ming Liu
  • Publication number: 20080025528
    Abstract: A noise reduction system is used in a BTSC system to reduce noise of an audio signal. The noise reduction system has an audio spectral compressing unit that has a filter and a memory in the approach of the digital processing. The filter is arranged to filter an input signal according to a transfer function, a variable d, and several parameters b0/a0, a0/b0, b1/b0 and a1/a0. The memory is arranged to store the parameters.
    Type: Application
    Filed: July 27, 2006
    Publication date: January 31, 2008
    Applicant: Himax Technologies, Inc.
    Inventors: Kai-Ting Lee, Tien-Ju Tsai
  • Publication number: 20080008187
    Abstract: A transmission convergence sublayer circuit is coupled between a buffer and a deframer. The deframer submits a data stream enable signal and data bytes to the circuit. The data stream enable signal enables the circuit so that multiple groups of byte data belonging to a data cell are received and temporarily stored inside a byte-wise data pipeline. A header cyclic redundancy checker also receives the byte data and then conducts a header search. An idle cell identifier is used to determine if the data cell is a non-idle cell. When the header is found and determined to be a non-idle cell, a descrambler retrieves payload data of data cell from the byte-wise data pipeline and conducts a descrambling operation after obtaining a quantity of data equal to a double word. Ultimately, the double word data is output to the buffer with minimum delay.
    Type: Application
    Filed: September 20, 2007
    Publication date: January 10, 2008
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Tien-Ju Tsai, Chih-Feng Lin
  • Patent number: 7280544
    Abstract: Transmission convergence sublayer circuit is coupled between a buffer and a deframer. The deframer submits a data stream enable signal and data bytes to the circuit. The data stream enable signal enables the circuit so that multiple groups of byte data belonging to a data cell are received and temporarily stored inside a byte-wise data pipeline. A header cyclic redundancy checker also receives the byte data and then conducts a header search. An idle cell identifier is used to determine if the data cell is a non-idle cell. When the header is found and determined to be a non-idle cell, a descrambler retrieves payload data of data cell from the byte-wise data pipeline and conducts a descrambling operation after obtaining a quantity of data equal to a double word. Ultimately, the double word data is output to the buffer with minimum delay.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: October 9, 2007
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Tien-Ju Tsai, Chih-Feng Lin
  • Publication number: 20070211903
    Abstract: A decimator is used to process a multi-channel audio signal, and includes a memory, a controller and a processing unit. The processing unit is used to decimate each input audio component of a multi-channel audio signal to generate corresponding multi-channel operational data. The controller is used to control read and write actions for each audio component of the multi-channel audio signal and the multi-channel operational data into or from the memory. The memory provides a digital signal process for decimation together with the processing unit. The input of the multi-channel audio and the output of the multi-channel operational data are performed through time division. Compared with conventional decimator circuits, the decimator circuit of the present invention reduces the cost and the power consumption of the hardware circuitry.
    Type: Application
    Filed: March 6, 2007
    Publication date: September 13, 2007
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Tien Ju Tsai, Chao Wei Huang
  • Publication number: 20040179478
    Abstract: A physical layer with power off alert (POA) and the alerting method thereof. It uses a power detector to detect the power supplied to the physical layer, and uses a POA packet generator to generate a POA packet when the supplied power is off. Therefore, it can use the POA packet transmitted on the network to notify the user of the opposite nodes or other nodes on the network.
    Type: Application
    Filed: June 2, 2003
    Publication date: September 16, 2004
    Inventors: Chieh-Yuan Ke, Tsu-Chun Liu, Tien-Ju Tsai, Chung-Cheng Chen, Jean-Ming Lee, Kun-Che Chung
  • Publication number: 20040174819
    Abstract: A physical layer with smart cable analyzing (SCA) and the apparatus employing the same. When poor quality is possibly found in the cable connecting to the physical layer, its loop back controller is used to control the timing for entering into the loop back test mode, so as to analyze the cable quality and assist the user to exclude the root cause of the problem.
    Type: Application
    Filed: June 2, 2003
    Publication date: September 9, 2004
    Inventors: Tsu-Chun Liu, Chieh-Yuan Ke, Chung-Cheng Chen, Tien-Ju Tsai, Jean-Ming Lee, Kun-Che Chung
  • Publication number: 20030048803
    Abstract: A transmission convergence sublayer circuit and operating method for an asynchronous transfer receiver. The transmission convergence sublayer circuit is coupled between a buffer and a deframer. The deframer submits a data stream enable signal and data bytes to the circuit. The data stream enable signal enables the circuit so that multiple groups of byte data belonging to a data cell are received and temporarily stored inside a byte-wise data pipeline. A header cyclic redundancy checker also receives the byte data and then conducts a header search. An idle cell identifier is used to determine if the data cell is a non-idle cell. When the header is found and determined to be a non-idle cell, a descrambler retrieves payload data of data cell from the byte-wise data pipeline and conducts a descrambling operation after obtaining a quantity of data equal to a double word. Ultimately, the double word data is output to the buffer with minimum delay.
    Type: Application
    Filed: July 9, 2002
    Publication date: March 13, 2003
    Inventors: Tien-Ju Tsai, Chih-Feng Lin