Patents by Inventor Tim J. Corbett

Tim J. Corbett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5539324
    Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical test equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical test are completed. After burn-in stress and electrical test, it is possible to establish interconnection between the single dice or separate and package the dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.
    Type: Grant
    Filed: November 24, 1992
    Date of Patent: July 23, 1996
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett
  • Patent number: 5302891
    Abstract: A reusable burn-in/test fixture for discrete die consists of two halves. The first half of the test fixture contains cavity in which die is inserted. When the two halves are assembled, the fixture establishes electrical contact with the die and with a burn-in oven. The test fixture need not be opened until the burn-in and electrical test are completed. The fixture permits the die to be characterized prior to assembly.
    Type: Grant
    Filed: November 10, 1992
    Date of Patent: April 12, 1994
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett, Gary L. Chadwick, Chender Huang, Larry D. Kinsman
  • Patent number: 5138434
    Abstract: A logic module design is disclosed which incorporates an unencapsulated wafer section or sections. The disclosed module is an improvement over previous designs in that it is less expensive and easier to manufacture due to the reduced number of components and the complexity of the components, is faster and consumes less power because of its shorter trace lengths and smaller size, and is more reliable as a result of its greatly reduced number of interconnects.
    Type: Grant
    Filed: January 22, 1991
    Date of Patent: August 11, 1992
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Tim J. Corbett
  • Patent number: 4992849
    Abstract: A leadframe interconnect package is tape automated bond (TAB) bonded to circuitry on the chip and which provides a circuit connection for subsequent connection to a printed circuit board.The configuration of integrated circuit chips mounted onto TAB circuitry and then encapsulated permits a variety of cooperative functions to be performed by a single lead attached chip assembly, even though multiple chips are used in the circuit.
    Type: Grant
    Filed: February 15, 1989
    Date of Patent: February 12, 1991
    Assignee: Micron Technology, Inc.
    Inventors: Tim J. Corbett, Alan G. Wood
  • Patent number: 4992850
    Abstract: A leadframe interconnect package is tape automated bond (TAB) bonded to circuitry on the chip and which provides a circuit connection for subsequent connection to a printed circuit board. The encapsulated chips will replace both the leadframe and printed circuit board (electrical only) as we now know it in the conventional SIMM module.
    Type: Grant
    Filed: February 15, 1989
    Date of Patent: February 12, 1991
    Assignee: Micron Technology, Inc.
    Inventors: Tim J. Corbett, Alan G. Wood
  • Patent number: 4899107
    Abstract: A reusable burn-in/test fixture for discrete TAB die consists of two halves. The first half of the test fixture is a die cavity plate for receiving semiconductor dice, and contains cavities in which die are inserted. The second half establishes electrical contact with the dice and with a burn-in oven. The test fixture need not be opened until the burn-in and electrical test are completed. After burn-in stress and electrical test, the die are removed from the test fixture and depositioned accordingly. The technique will allow all elements of the burn-in/test fixture to 100% reusable.
    Type: Grant
    Filed: September 30, 1988
    Date of Patent: February 6, 1990
    Assignee: Micron Technology, Inc.
    Inventors: Tim J. Corbett, Alan G. Wood