Patents by Inventor Ting Liu

Ting Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230118769
    Abstract: A sequence detection device includes a decision-feedback equalizer (DFE), a combining circuit, a decision circuit, and a sequence detection circuit. The DFE processes a symbol decision signal to generate a first equalized signal. The combining circuit combines a data signal and the first equalized signal to generate a sample signal. The decision circuit performs hard decision upon the sample signal to generate the symbol decision signal. The sequence detection circuit performs sequence detection upon the data signal to generate and output a symbol sequence. Regarding the sequence detection, the sequence detection circuit selects branches for branch metric calculation according to at least the symbol decision signal.
    Type: Application
    Filed: August 22, 2022
    Publication date: April 20, 2023
    Applicant: MEDIATEK INC.
    Inventors: Yu-Ting Liu, Che-Yu Chiang, Deng-Fu Weng
  • Patent number: 11632346
    Abstract: A device, such as a head-mounted wearable device (HMWD), provides audible notifications to a user with a voice user interface (VUI). A filtered subset of notifications addressed to the user, such as notifications from contacts associated with specified applications, are processed by a text to speech system that generates audio output for presentation to the user. The audio output may be presented using the HMWD. For example, the audio output generated from a text message received from a contact may be played on the device. The user may provide an input to play the notification again, initiate a reply, or take another action. The input may comprise a gesture on a touch sensor, activation of a button, verbal input acquired by a microphone, and so forth.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: April 18, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Abinash Mahapatra, Anuj Saluja, Ouning Zhang, Xinyu Miao, Ting Liu, Yanina Potashnik, Alfred Ying Fai Lui, Choon-Mun Hooi, Jeffrey John Easter, Oliver Huy Doan, Jonathan B. Assayag
  • Patent number: 11630169
    Abstract: In one aspect, a method includes forming a metal layer on a substrate, wherein the metal layer comprises a first coil, forming a planarized insulator layer on the metal layer, forming at least one via in the planarized insulator layer, depositing a magnetoresistance (MR) element on the planarized insulator layer, and forming a second coil extending above the MR element. The at least one via electrically connects to the metal layer on one end and to MR element on the other end.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: April 18, 2023
    Assignee: Allegro MicroSystems, LLC
    Inventors: Yen Ting Liu, Maxim Klebanov, Paolo Campiglio, Sundar Chetlur, Harianto Wong
  • Publication number: 20230104442
    Abstract: A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.
    Type: Application
    Filed: December 9, 2022
    Publication date: April 6, 2023
    Inventors: Yen-Tien Tung, Szu-Wei Huang, Zhi-Ren Xiao, Yin-Chuan Chuang, Yung-Chien Huang, Kuan-Ting Liu, Tzer-Min Shen, Chung-Wei Wu, Zhiqiang Wu
  • Publication number: 20230089728
    Abstract: A polyphenylene ether resin modified with benzoxazine, a method for producing the same, and a substrate material for a circuit board are provided. The polyphenylene ether resin modified with the benzoxazine has a structural formula as follows: in which R represents a chemical group that is located between two hydroxyphenyl functional groups of a bisphenol compound, and n is an integer between 3 and 25, inclusive.
    Type: Application
    Filed: July 24, 2022
    Publication date: March 23, 2023
    Inventors: TE-CHAO LIAO, HUNG-YI CHANG, YU-TING LIU, CHIEN-KAI WEI, Chi-Lin Chen
  • Publication number: 20230090736
    Abstract: A polyphenylene ether resin modified with two amino functional groups, a method for producing the same, and a substrate material for a circuit board are provided. The polyphenylene ether resin modified with the two amino functional groups has a structural formula as follows: in which R represents a chemical group that is located between two hydroxyphenyl functional groups of a bisphenol compound, and n is an integer between 3 and 25, inclusive.
    Type: Application
    Filed: August 15, 2022
    Publication date: March 23, 2023
    Inventors: TE-CHAO LIAO, HUNG-YI CHANG, YU-TING LIU, CHUNG-YU CHEN, CHIA-RUEY TSAI, JUNG-TSU WU, CHIEN-KAI WEI
  • Publication number: 20230091594
    Abstract: A polyphenylene ether resin modified with bismaleimide, a method for producing the same, and a substrate material for a circuit board are provided. The polyphenylene ether resin modified with the bismaleimide has a structural formula as follows: in which R represents a chemical group that is located between two hydroxyphenyl functional groups of a bisphenol compound, and n is an integer between 3 and 25, inclusive.
    Type: Application
    Filed: June 27, 2022
    Publication date: March 23, 2023
    Inventors: TE-CHAO LIAO, HUNG-YI CHANG, YU-TING LIU, CHIEN-KAI WEI, Chi-Lin Chen
  • Patent number: 11605819
    Abstract: A battery, having polyvalent aluminum metal as the electrochemically active anode material and also including a solid ionically conducting polymer material.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: March 14, 2023
    Assignee: IONIC MATERIALS, INC.
    Inventors: Michael A. Zimmerman, Alexei B. Gavrilov, Ting Liu, Keith Smith
  • Publication number: 20230075646
    Abstract: A rotating mechanism includes a main shaft assembly, a first fastening bracket, a first transmission arm, a first rotation arm, a first support plate, a second fastening bracket, a second transmission arm, a second rotation arm, and a second support plate. One end of the first transmission arm is slidably connected to the first fastening bracket, and the other end is rotatably connected to the main shaft assembly. Two ends of the first rotation arm are rotatably connected to the first fastening bracket and the main shaft assembly respectively.
    Type: Application
    Filed: April 15, 2021
    Publication date: March 9, 2023
    Inventors: Linhui Niu, Chunjun Ma, Zhengyi Xu, Ting Liu, Yungyong Li, Gangchao Wang
  • Publication number: 20230077312
    Abstract: The application relates to a method for manufacturing an electronic device, and in particular, to a method for manufacturing an electronic device with a carrier substrate. The method includes: providing a carrier; forming a first base layer on the carrier; and forming working units on the first base layer. The working units are spaced apart from one another.
    Type: Application
    Filed: October 22, 2021
    Publication date: March 9, 2023
    Inventors: Yeong-E CHEN, Cheng-En CHENG, Yu-Ting LIU, Cheng-Chi WANG
  • Patent number: 11598830
    Abstract: Methods and apparatus for a sensor including a series of tunneling magnetoresistance (TMR) pillars and a heatsink adjacent to at least one of the TMR pillars, where the heatsink comprises Titanium Nitride (TiN).
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: March 7, 2023
    Assignee: Allegro MicroSystems, LLC
    Inventors: Sundar Chetlur, Maxim Klebanov, Yen Ting Liu, Paolo Campiglio
  • Publication number: 20230067745
    Abstract: The present disclosure is directed to an in situ closed-loop radio frequency (RF) power management on RF processes such as a plasma etch process, a plasma chemical vapor deposition process, a plasma physical vapor deposition process, a plasma clean process, or the like. An RF power measurement device according to one or more embodiments of the present disclosure assists the in situ closed-loop RF power management on RF processes. In some embodiments, the RF power measurement device includes a coil-shaped current sensor that is wound around the path between an RF generator and a chamber. The coil-shaped current sensor senses the current flowing through this path so that the power of the RF generator may be calibrated without having to separate the RF generator for separate analysis and calibration. The RF power measurement device allows management of RF power in an in situ closed-loop manner.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Wei Ting LIU, Wen-Wei FAN
  • Patent number: 11594610
    Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hang Chiu, Chung-Chiang Wu, Jo-Chun Hung, Wei-Cheng Wang, Kuan-Ting Liu, Chi On Chui
  • Publication number: 20230056817
    Abstract: A cryogenic system cools and operates cryogenic electronics. The cryogenic system includes a cryogenic stage or multiple cryogenic stages for cooling the cryogenic electronics to an operational cryogenic temperature. The cryogenic stage or stages transfer heat from the cryogenic electronics to an ambient environment. An optical fiber or multiple optical fibers deliver an operational power from the ambient environment to the cryogenic electronics and transfer communication data between the cryogenic electronics and the ambient environment. Preferably, the only connection delivering any power from the ambient environment to the cryogenic electronics or transferring any data from the cryogenic electronics to the ambient environment is the optical fiber or fibers, such that the cryogenic system does not include any electrically conductive wires spanning between the ambient environment and the cryogenic electronics.
    Type: Application
    Filed: August 20, 2021
    Publication date: February 23, 2023
    Inventors: Brad Chun-Ting Liu, Sergio A. Montoya, Saurabh Sharma, Carlos Torres, JR., Marico C. de Andrade, Michael C. O'Brien
  • Patent number: 11585357
    Abstract: A fan casing for mounting of a fan includes a frame including four corner segments and four side segments that are arranged alternately with the corner segments, a seat disposed in the frame, and four support members extending radially and outwardly from the seat and connected respectively to the corner segments. Each support member includes a base connected to the seat and having a width reducing in a direction away from the seat, and a rib connected between the base and the corresponding corner segment. The bases are interconnected to surround the seat. Any two adjacent bases are interconnected to form an arc surface facing the corresponding side segment and adapted to absorb shock.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: February 21, 2023
    Assignee: YEN SUN TECHNOLOGY CORP.
    Inventors: Graham Chen, Chih-Tsung Hsu, Hsin-Hsien Wu, Chin-Hui Pan, Yu-Ting Liu
  • Publication number: 20230050018
    Abstract: The present invention provides a QFN packaging structure and QFN packaging method. By providing the insulating layer on the outer side of the leads of the QFN packaging structure, a short circuit between the leads and the electromagnetic shielding layer can be prevented. In addition, the grounding lead is exposed from the insulating layer, such that the electromagnetic shielding layer is grounded via the grounding lead, thereby realizing the electromagnetic shielding design of the QFN packaging structure.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 16, 2023
    Inventors: YUN GAO, TING LIU, YUESHENG ZHANG, RONG FAN
  • Publication number: 20230048687
    Abstract: The present invention provides a QFN packaging structure and QFN packaging method. The electromagnetic shielding layer as provided on the outer side of the QFN packaging structure by spacing at a certain interval from the leads may cooperate with the base island having the lug boss on the side edge, such that all surfaces of the chip can be electromagnetically shielded and protected while ensuring the insulation between the electromagnetic shielding layer and the leads.
    Type: Application
    Filed: August 12, 2022
    Publication date: February 16, 2023
    Inventors: YUN GAO, TING LIU, YUESHENG ZHANG, HONGHAO SHI
  • Publication number: 20230050951
    Abstract: A display device includes a pixel array substrate and a circuit board. The pixel array substrate has a first surface, a second surface opposite to the first surface, and a first side surface connecting the first surface and the second surface. Multiple bonding pads are located on the first surface. The circuit board is bent from above the first surface of the pixel array substrate to below the second surface. The circuit board is electrically connected to the bonding pads and includes a thermoplastic substrate. The thermoplastic substrate includes a third surface facing the pixel array substrate and a fourth surface opposite to the third surface. The thermoplastic substrate includes a first bend formed by thermoplastics.
    Type: Application
    Filed: November 1, 2021
    Publication date: February 16, 2023
    Applicant: Au Optronics Corporation
    Inventors: Wei-Fu Wu, Yu Tseng, Yu-Ting Liu, Chih-Cheng Kao, Tsai-Chi Yeh
  • Patent number: 11582865
    Abstract: A package device and a manufacturing method thereof are provided. The package device includes a redistribution layer including a first dielectric layer, a conductive layer, and a second dielectric layer. The conductive layer is disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test mark, the test mark includes a plurality of conductive patterns formed of the conductive layer, and the conductive patterns are arranged in a ring shape.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: February 14, 2023
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Cheng-En Cheng, Yu-Ting Liu
  • Patent number: 11579099
    Abstract: This disclosure relates to an apparatus and methods for applying X-ray reflectometry (XRR) in characterizing three dimensional nanostructures supported on a flat substrate with a miniscule sampling area and a thickness in nanometers. In particular, this disclosure is targeted for addressing the difficulties encountered when XRR is applied to samples with intricate nanostructures along all three directions, e.g. arrays of nanostructured poles or shafts. Convergent X-ray with long wavelength, greater than that from a copper anode of 0.154 nm and less than twice of the characteristic dimensions along the film thickness direction, is preferably used with appropriate collimations on both incident and detection arms to enable the XRR for measurements of samples with limited sample area and scattering volumes.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: February 14, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Ting Liu, Wen-Li Wu, Bo-Ching He, Guo-Dung Chen, Sheng-Hsun Wu, Wei-En Fu