Patents by Inventor Ting Liu

Ting Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11779282
    Abstract: The present invention discloses a method for determining a degree of response to a physical activity. Acquire a physical activity signal measured by a sensing unit in the physical activity. Determine first data of a first physical activity feature set based on the physical activity signal. Determine a recognition of the degree of response to the physical activity based on the first data of the first physical activity feature set by a mathematical model describing a relationship between the first physical activity feature set and the degree of response to a physical activity. A portion of a first mechanism of the mathematical model adopts at least one portion of a second mechanism of a first neural network model associated with the second physical activity feature set.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: October 10, 2023
    Assignee: BOMDIC, INC.
    Inventors: Hao-Yi Chih, Yu-Ting Liu, Amy Pei-Ling Chiu
  • Publication number: 20230316560
    Abstract: A tracking apparatus, method, and non-transitory computer readable storage medium thereof are provided. The tracking apparatus generates a map information of simultaneous localization and mapping corresponding to a regional space based on a real-time image. The tracking apparatus calculates a first spatial position and a first orientation of a first display related to the image capturing device in the regional space based on the map information. The tracking apparatus calculates a human pose of a first operating user in the regional space. The tracking apparatus transforms the real-time image to generate a first transformed image corresponding to the first operating user based on the first spatial position, the first orientation, and the human pose, wherein the first transformed image is displayed on the first display.
    Type: Application
    Filed: March 27, 2023
    Publication date: October 5, 2023
    Inventors: Yen-Ting LIU, Meng-Ju WU
  • Publication number: 20230319111
    Abstract: A processing blade is assigned from the plurality of processing blades to a session of data packets. The load balancing engine manages a session table and an IPsec routing table by updating the session table with a particular security engine card assigned to the session and by updating the IPsec routing table for storing a remote IP address for a particular session. Outbound raw data packets of a particular session are parsed for matching cleartext tuple information prior to IPsec encryption, and inbound encrypted data packets of the particular session are parsed for matching cipher tuple information prior to IPsec decryption. Inbound data packets assigned to the processing blade from the session table are parsed and forwarded to the station.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Inventors: Yita Lee, Sen Yang, Ting Liu
  • Publication number: 20230317799
    Abstract: A method according to the present disclosure includes providing a substrate that includes a dummy gate stack wrapping over an active region, and a spacer layer extending along sidewalls of the dummy gate stack, selectively removing the dummy gate stack to form a gate trench exposing the active region, depositing a gate dielectric over the active region, depositing at least one work function layer over the gate dielectric layer, depositing a tungsten layer over the at least one work function layer, and depositing a tungsten nitride layer over the tungsten layer.
    Type: Application
    Filed: May 23, 2022
    Publication date: October 5, 2023
    Inventors: Shih-Hang Chiu, Wei-Cheng Wang, Kuan-Ting Liu, Chi On Chui
  • Patent number: 11776914
    Abstract: A package device is provided and includes a redistribution layer. The redistribution layer includes a first dielectric layer, a second dielectric layer, and a conductive layer. The second dielectric layer is disposed on the first dielectric layer, and the second dielectric layer includes a dielectric pattern. The conductive layer is disposed between the first dielectric layer and the second dielectric layer, and the conductive layer includes a first conductive pattern. The dielectric pattern has a through hole, and in a top view of the package device, the first conductive pattern and the through hole are overlapped with each other.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: October 3, 2023
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Cheng-En Cheng, Yu-Ting Liu
  • Patent number: 11772858
    Abstract: An airtight device includes a container and an airtight cover on the container, and the airtight cover includes a fixing bracket, a door, and a pressuring handle. The fixing bracket has a through hole and a guiding slot, and the through hole communicates with internal space of the container. The guiding slot has adjacent first and second top surfaces, and the second top surface is higher than the first top surface. The door selectively covers the through hole. The pressuring handle pivoted on the door has a first section, a second section, and a rotating axis between the first and second sections, and the first section rotates relative to the second section. The second section receives a force to drive the first section to move from below the second top surface to below the first top surface such that the rotating axis pressures the door.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: October 3, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chia-Hsing Chen, Chiu-Chin Chang, Yan-Hui Jian, Chih-Jui Chen, Chen-Hsiu Lee, Hsuan-Ting Liu, Chin-Lung Liu, Kuan-Lung Wu, Li-Hsiu Chen, Wen-Yin Tsai
  • Publication number: 20230308322
    Abstract: An error detection and correction device includes a decision-feedback equalizer (DFE), a decision circuit, an error detection circuit, and an error correction circuit. The DFE equalizes a data signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a symbol decision signal. The error detection circuit performs forward error detection at symbol positions of consecutive symbols included in the symbol decision signal to detect a head position of suspicious error that affects at least one symbol in the symbol decision signal. The error correction circuit performs error correction upon the symbol decision signal in response to the head position of the suspicious error that is detected by the error detection circuit.
    Type: Application
    Filed: March 2, 2023
    Publication date: September 28, 2023
    Applicant: MEDIATEK INC.
    Inventors: Deng-Fu Weng, Yu-Ting Liu, Che-Yu Chiang, Chung-Hsien Tsai, Huai-Mao Weng
  • Publication number: 20230307347
    Abstract: The present disclosure provides an electronic device including a substrate, a first pad, an insulating layer, a second pad, a conductive element and a chip. The first pad is disposed on the substrate. The insulating layer is disposed on the first pad and has a plurality of first openings. The second pad is electrically connected to the first pad through the first openings. The conductive particle is disposed on the second pad. The chip is electrically connected to the second pad through the conductive element. In a top view of the electronic device, the first openings are arranged along a long edge of the first pad, and an outline of at least one first opening has a curved shape.
    Type: Application
    Filed: June 1, 2023
    Publication date: September 28, 2023
    Applicant: InnoLux Corporation
    Inventors: Mei-Chi Hsu, Yu-Chin Lin, Yu-Ting Liu
  • Publication number: 20230307891
    Abstract: A semiconductor layer structure may include a substrate, a blocking layer disposed over the substrate, and one or more epitaxial layers disposed over the blocking layer. The blocking layer may have a thickness of between 50 nanometers (nm) and 4000 nm. The blocking layer may be configured to suppress defects from the substrate propagating to the one or more epitaxial layers. The one or more epitaxial layers may include a quantum-well layer that includes a quantum-well intermixing region formed using a high temperature treatment.
    Type: Application
    Filed: May 31, 2023
    Publication date: September 28, 2023
    Inventors: Ting LIU, Xing LI, Hery DJIE
  • Patent number: 11761022
    Abstract: Disclosed are methods of releasing or enriching for steviol glycosides produced by yeast. The disclosed methods enhance or improve the release or enrichment of the steviol glycosides.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: September 19, 2023
    Assignee: CARGILL, INCORPORATED
    Inventors: James C. Anderson, Robert J. Brower, III, Ting Liu Carlson, Belit Flores, Dan S. Gaspard, Kristopher T. Mortenson, Richard Nygaard, Nicole Paulson, Maribeth Rasmussen
  • Publication number: 20230292629
    Abstract: A method for forming a semiconductor memory structure includes forming an MTJ stack over a substrate. The method also includes etching the MTJ stack to form an MTJ device. The method also includes depositing a metal layer over a top surface and sidewalls of the MTJ device. The method also includes oxidizing the metal layer to form an oxidized metal layer. The method also includes depositing a cap layer over the oxidized metal layer. The method also includes oxidizing the cap layer to form an oxidized cap layer. The method also includes removing an un-oxidized portion of the cap layer.
    Type: Application
    Filed: March 9, 2022
    Publication date: September 14, 2023
    Inventors: Tzu-Ting LIU, Yu-Jen WANG, Chih-Pin CHIU, Hung-Chao KAO, Chih-Chuan SU, Liang-Wei WANG, Chen-Chiu HUANG, Dian-Hau CHEN
  • Patent number: 11739353
    Abstract: Disclosed are methods for producing steviol glycosides, such as rebaudioside D and rebaudioside M, using engineered yeast. The methods include at least two phases: first and second phases where a glucose-containing feed composition is provided to the medium in different modes of feeding in each phase, such as variable feeding and then constant feeding. The two phase feeding can result in a growth rate that is slower in the second phase than in the first phase, and consequently increased steviol glycoside production rates, reduced fermentation times, and reduced biomass concentrations.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: August 29, 2023
    Assignee: Cargill, Incorporated
    Inventors: James C. Anderson, Ting Liu Carlson, Arlene M. Fosmer
  • Publication number: 20230263201
    Abstract: Sweetener compositions comprising particular glycoside blends are described in this paper. The glycioside blends comprise rebaudioside A, rebaudioside B, and/or rebaudioside D in various proportions. The sweetener composition can also include one or more bulking agents or other ingredients. The sweetener compositions can be used in foods and beverages.
    Type: Application
    Filed: October 5, 2022
    Publication date: August 24, 2023
    Applicant: CARGILL, INCORPORATED
    Inventors: Ting Liu CARLSON, Brian D. GUTHRIE, Timothy Alan LINDGREN, Michael Alan MORTENSON
  • Publication number: 20230260825
    Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.
    Type: Application
    Filed: February 14, 2022
    Publication date: August 17, 2023
    Inventors: He REN, Houssam LAZKANI, Raman GAIRE, Mehul NAIK, Kuan-Ting LIU
  • Patent number: 11719771
    Abstract: Methods and apparatus for a magnetoresistive (MR) sensor including a seed layer having a CoFe layer for canceling hysteresis in the MR sensor. The MR stackup can include a free layer and a reference layer. The seed layer having CoFe provides a desired texturing of the stackup to cancel hysteresis effects.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: August 8, 2023
    Assignee: Allegro MicroSystems, LLC
    Inventors: Paolo Campiglio, Samridh Jaiswal, Yen Ting Liu, Maxim Klebanov, Sundar Chetlur
  • Publication number: 20230240537
    Abstract: A calibration device for an intraoral scanner is provided. The calibration device includes a base, a moving portion, a circuit board, and a sensor. The moving portion is disposed on the base. The moving portion is moveable on the base along an extending direction of the calibration device. The moving portion includes a driving structure, a position determining portion, and a target plate. The position determining portion is coupled to and driven by the driving structure. The position determining portion has a first feature portion and a second feature portion different from the first feature portion. The target plate is coupled to the position determining portion. The circuit board is disposed at one side of the moving portion. The sensor is disposed on the circuit board. The sensor is configured to detect the first feature portion and the second feature portion to determine a position of the moving portion.
    Type: Application
    Filed: May 11, 2022
    Publication date: August 3, 2023
    Applicant: Qisda Corporation
    Inventors: Tsung-Hsun WU, Ching-Ting LIU, Yuan-Yu HSIAO
  • Publication number: 20230228828
    Abstract: In one aspect, a method includes forming a coil in a coil layer, performing planarization on the coil layer, and depositing a magnetoresistance (MR) element on the planarized coil layer. No dielectric material is between the planarized coil layer and the MR element. In another aspect, a magnetic field sensor includes a substrate, a planarized coil layer comprising a coil on the substrate, a magnetoresistance (MR) element in contact with the planarized coil layer, and a capping layer deposited over the MR element and the planarized coil layer. No dielectric material is between the planarized coil layer and the MR element.
    Type: Application
    Filed: January 17, 2022
    Publication date: July 20, 2023
    Applicant: Allegro MicroSystems, LLC
    Inventors: Maxim Klebanov, Yen Ting Liu, Paolo Campiglio, Sundar Chetlur, Harianto Wong
  • Publication number: 20230226411
    Abstract: A speed generation method for simulating riding is provided. A computer device (20) retrieves a riding weight and road condition information, selects one of a plurality of preset gear ratios (30) as a selected gear ratio, retrieves a wheel rotating speed of a bicycle (4), and determines a simulated speed in a simulating riding service based on the selected gear ratio, a tire parameter, and the rotating speed.
    Type: Application
    Filed: December 6, 2022
    Publication date: July 20, 2023
    Inventors: Chun-Cheng CHEN, Chun-Ting LIU, Sung-Yi CHUANG
  • Publication number: 20230230914
    Abstract: The present disclosure provides an electronic device including a substrate, an extending element, a conductive element and a first insulating layer. The substrate includes an edge. The extending element is disposed on the substrate and includes a first conductive layer and a semiconductor layer, the first conductive layer and the semiconductor layer are overlapped, and the semiconductor layer extends to the edge of the substrate. The conductive element is overlapped with the first conductive layer. The insulating layer is disposed between the conductive element and the extending element.
    Type: Application
    Filed: March 16, 2023
    Publication date: July 20, 2023
    Applicant: InnoLux Corporation
    Inventors: Chiu-Yuan Huang, Pei-Chieh Chen, Yu-Ting Liu, Tsung-Yeh Ho
  • Publication number: 20230230497
    Abstract: A virtual reality system with an inspecting function of assembling and disassembling and an inspection method of assembling and disassembling based on virtual reality are presented. A learning-end acquires an inspection data and a teaching assembling-disassembling record being set with a plurality of checkpoints, plays the teaching assembling-disassembling record, modifies a learning assembling-disassembling status of a plurality of virtual objects based on user's operations for assembling or disassembling. The learning-end issues an assembling-disassembling error reminder when the learning assembling-disassembling status is inconsistent with a teaching assembling-disassembling status at any of the checkpoints.
    Type: Application
    Filed: May 16, 2022
    Publication date: July 20, 2023
    Inventors: Yao-Han YEN, Wen-Hsin LO, Yu-Ting LIU, Guan-Jhih LIOU