Patents by Inventor Tomonori Aoyama

Tomonori Aoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130075844
    Abstract: A semiconductor device according to the present embodiment comprises a lower electrode provided above a semiconductor substrate and made of metal, an upper electrode provided above the lower electrode and made of metal, and a crystal layer provided between the lower electrode and the upper electrode. A thickness of each of the lower electrode and the upper electrode is smaller than a thickness of a skin layer deriving from a skin effect corresponding to a frequency of a microwave used to crystallize the crystal layer.
    Type: Application
    Filed: July 11, 2012
    Publication date: March 28, 2013
    Inventors: Kiyotaka Miyano, Tomonori Aoyama
  • Patent number: 8383452
    Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include depositing a first amorphous film having a first impurity, depositing a third amorphous lower-layer film on the first amorphous film, forming microcrystals on the third amorphous lower-layer film, depositing a third amorphous upper-layer film on the third amorphous lower-layer film to cover the microcrystals, depositing a second amorphous film having a second impurity on the third amorphous upper-layer film, and radiating microwaves to crystallize the third amorphous lower-layer film and the third amorphous upper-layer film to form a third crystal layer, and crystallize the first amorphous film and the second amorphous film to form a first crystal layer and a second crystal layer.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: February 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonori Aoyama, Kiyotaka Miyano, Yusuke Oshiki
  • Publication number: 20130023102
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a gate electrode on a channel region in a silicon substrate via a gate insulation film; forming a source region and a drain region in the silicon substrate so as to sandwich the channel region along a channel direction by injecting desired impurities to the silicon substrate; forming amorphous regions containing the impurities on surfaces of the source region and the drain region by amorphousizing the surfaces of the source region and the drain region; forming nickel films on the amorphous regions; and forming crystal layers containing the activated impurities and forming nickel silicide films on the crystal layers at low temperature by radiating microwaves to the amorphous regions and the nickel films.
    Type: Application
    Filed: March 8, 2012
    Publication date: January 24, 2013
    Inventors: Tomonori Aoyama, Kiyotaka Miyano, Hiroshi Nakazawa
  • Publication number: 20120273790
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming an amorphous semiconductor film on a substrate. The method further includes annealing the amorphous semiconductor film by irradiating the substrate with a microwave to form a polycrystalline semiconductor film from the amorphous semiconductor film. The method further includes forming a transistor whose channel is the polycrystalline semiconductor film.
    Type: Application
    Filed: March 8, 2012
    Publication date: November 1, 2012
    Inventors: Tomonori AOYAMA, Kiyotaka MIYANO
  • Publication number: 20120225498
    Abstract: According to one embodiment, a manufacturing method of semiconductor device includes forming plural elements on a substrate, forming a silicon compound film so as to bury between a plurality of elements, and modifying the silicon compound film to a silicon dioxide film by radiating microwaves.
    Type: Application
    Filed: September 30, 2011
    Publication date: September 6, 2012
    Inventors: Tomonori Aoyama, Kiyotaka Miyano
  • Patent number: 8198155
    Abstract: A semiconductor device according to an embodiment of the present invention includes an N-type transistor formed in a first region on a substrate, and a P-type transistor formed in a second region on the substrate.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: June 12, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Ikeno, Tomonori Aoyama, Kazuaki Nakajima, Seiji Inumiya, Takashi Shimizu, Takuya Kobayashi
  • Patent number: 8183641
    Abstract: A silicon oxynitride film is formed on entire surface of a semiconductor substrate, a lanthanum oxide film is formed on the silicon oxynitride film and the lanthanum oxide film is removed from a pMOS region. Then, a nitrided hafnium silicate film serving as a highly dielectric film is formed on the entire surface, an aluminum-containing titanium nitride film is formed, a polysilicon film is formed, and the stacked films are patterned into a gate electrode configuration. Next, impurities are introduced into a source/drain region, and an annealing for activating the impurities is utilized to diffuse the aluminum included in the aluminum-containing titanium nitride film to the interface between the silicon oxynitride film and the nitrided hafnium aluminum silicate film in the pMOS region.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: May 22, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Inumiya, Tomonori Aoyama
  • Patent number: 8174079
    Abstract: A semiconductor device includes a semiconductor substrate; a gate insulation film formed on the semiconductor substrate; a silicide gate electrode of an n-type MISFET formed on the gate insulation film; and a silicide gate electrode of a p-type MISFET formed on the gate insulation film and having a thickness smaller than that of the silicide gate electrode of the n-type MISFET, the silicide gate electrode of the p-type MISFET having a ratio of metal content higher than that of the silicide gate electrode of the n-type MISFET.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: May 8, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomonori Aoyama
  • Patent number: 8143676
    Abstract: A semiconductor device includes a substrate having first and second regions on a surface thereof, a first conductivity type first MISFET formed in the first region and a second conductivity type second MISFET formed in the second region. The first MISFET includes a silicon oxide film or a silicon oxynitride film formed on the surface of the substrate and a first insulating film which is formed in contact with the silicon oxide film or the silicon oxynitride film and which has a first element forming electric dipoles that reduce a threshold voltage of the first MISFET and the second MISFET includes a silicon oxide film or a silicon oxynitride film formed on the surface of the substrate, and a second insulating film which is formed in contact with the silicon oxide film or the silicon oxynitride film formed on the surface of the substrate and which has a second element forming electric dipoles in a direction opposite to that in the first MISFET.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: March 27, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Inumiya, Takuya Kobayashi, Tomonori Aoyama
  • Publication number: 20120045882
    Abstract: A semiconductor device manufacturing method includes: removing an insulating film on a semiconductor substrate by etching and subsequently oxidizing a surface of the semiconductor substrate by using a liquid oxidation agent without exposing this surface to an atmosphere, thereby forming a first insulating film containing an oxide of a constituent element of the semiconductor substrate on the surface of the semiconductor substrate; forming a second insulating film containing an aluminum oxide on the first insulating film; forming a third insulating film containing a rare earth oxide on the second insulating film; forming a high-k insulating film on the third insulating film; introducing nitrogen into the high-k insulating film to thereby make it a fourth insulating film; and conducting heat treatment to change the first through third insulating films into a insulating film made of a mixture containing aluminum, a rare earth element, the constituent element of the semiconductor substrate, and oxygen.
    Type: Application
    Filed: October 27, 2011
    Publication date: February 23, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Seiji Inumiya, Tomonori Aoyama
  • Publication number: 20120025200
    Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include depositing a first amorphous film having a first impurity, depositing a third amorphous lower-layer film on the first amorphous film, forming microcrystals on the third amorphous lower-layer film, depositing a third amorphous upper-layer film on the third amorphous lower-layer film to cover the microcrystals, depositing a second amorphous film having a second impurity on the third amorphous upper-layer film, and radiating microwaves to crystallize the third amorphous lower-layer film and the third amorphous upper-layer film to form a third crystal layer, and crystallize the first amorphous film and the second amorphous film to form a first crystal layer and a second crystal layer.
    Type: Application
    Filed: January 31, 2011
    Publication date: February 2, 2012
    Inventors: Tomonori Aoyama, Kiyotaka Miyano, Yusuke Oshiki
  • Patent number: 8093141
    Abstract: According to one embodiment, a method of fabricating a semiconductor device is disclosed. The method can include forming an amorphous layer on a portion of a first silicon substrate having a first plane orientation, and irradiating with micro wave on the amorphous layer to transform from the amorphous layer into a crystalline layer having the first plane orientation.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: January 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonori Aoyama, Kiyotaka Miyano
  • Patent number: 8071447
    Abstract: A semiconductor device manufacturing method includes removing an insulating film on a semiconductor substrate by etching and subsequently oxidizing a surface of the substrate by using a liquid oxidation agent without exposing this surface to an atmosphere, thereby forming a first insulating film containing an oxide of a constituent element of the substrate on the surface of the substrate; forming a second insulating film containing an aluminum oxide on the first insulating film; forming a third insulating film containing a rare earth oxide on the second insulating film; forming a high-k insulating film on the third insulating film; introducing nitrogen into the high-k insulating film to thereby make it a fourth insulating film; and conducting heat treatment to change the first through third insulating films into an insulating film made of a mixture containing aluminum, a rare earth element, the constituent element of the substrate, and oxygen.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: December 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Inumiya, Tomonori Aoyama
  • Patent number: 8039333
    Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a SiGe crystal layer on a semiconductor substrate, the SiGe crystal layer having a first plane and a second plane inclined with respect to the first plane; forming an amorphous Si film on the SiGe crystal layer; crystallizing a portion located adjacent to the first and second planes of the amorphous Si film by applying heat treatment using the first and second planes of the SiGe crystal layer as a seed, thereby forming a Si crystal layer; selectively removing or thinning a portion of the amorphous Si film that is not crystallized by the heat treatment; applying oxidation treatment to a surface of the Si crystal layer, thereby forming a gate insulating film on the surface of the Si crystal layer; and forming a gate electrode on the gate insulating film.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: October 18, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Kaneko, Seiji Inumiya, Tomonori Aoyama, Takuya Kobayashi
  • Patent number: 8022486
    Abstract: A semiconductor device includes a semiconductor substrate, and a p-channel MOS transistor provided on the semiconductor substrate, the p-channel MOS transistor comprising a first gate dielectric film including Hf, a second gate dielectric film provided on the first gate dielectric film and including aluminum oxide, and a first metal silicide gate electrode provided on the second gate dielectric film.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: September 20, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Tomonori Aoyama, Takuya Kobayashi
  • Publication number: 20110215333
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device, wherein an amorphous semiconductor film comprising a microcrystal is annealed using a microwave, to crystallize the amorphous semiconductor film comprising the microcrystal using the microcrystal as a nucleus.
    Type: Application
    Filed: September 16, 2010
    Publication date: September 8, 2011
    Inventors: Tomonori AOYAMA, Yusuke Oshiki, Kiyotaka Miyano
  • Patent number: 7989896
    Abstract: A method of fabricating a semiconductor device according to one embodiment includes: laying out a first region, a second region, a third region and a fourth region on a semiconductor substrate by forming an element isolation region in the semiconductor substrate; forming a first insulating film on the first region and the second region; forming a first semiconductor film on the first insulating film; forming a second insulating film and an aluminum oxide film thereon on the fourth region after forming of the first semiconductor film; forming a third insulating film and a lanthanum oxide film thereon on the third region after forming of the first semiconductor film; forming a high dielectric constant film on the aluminum oxide film and the lanthanum oxide film; forming a metal film on the high dielectric constant film; forming a second semiconductor film on the first semiconductor film and the metal film; and patterning the first insulating film, the first semiconductor film, the second insulating film, the al
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: August 2, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonori Aoyama, Seiji Inumiya, Kazuaki Nakajima, Takashi Shimizu
  • Publication number: 20110111580
    Abstract: According to one embodiment, a method of fabricating a semiconductor device is disclosed. The method can include forming an amorphous layer on a portion of a first silicon substrate having a first plane orientation, and irradiating with micro wave on the amorphous layer to transform from the amorphous layer into a crystalline layer having the first plane orientation.
    Type: Application
    Filed: September 9, 2010
    Publication date: May 12, 2011
    Inventors: Tomonori AOYAMA, Kiyotaka Miyano
  • Publication number: 20110076842
    Abstract: An ion implantation is performed to implant ions into a silicon substrate, and a microwave irradiation is performed to irradiate the silicon substrate with microwaves after the ion implantation. After the microwave irradiation, the silicon substrate is transferred to a heat-treatment apparatus, where the silicon substrate is treated with heat by being irradiated with light having a pulse width ranging from 0.1 milliseconds to 100 milliseconds, both inclusive.
    Type: Application
    Filed: September 30, 2010
    Publication date: March 31, 2011
    Inventors: Kenichi YOSHINO, Kiyotaka Miyano, Tomonori Aoyama
  • Publication number: 20110062528
    Abstract: A semiconductor device includes a semiconductor substrate; a gate insulation film formed on the semiconductor substrate; a silicide gate electrode of an n-type MISFET formed on the gate insulation film; and a silicide gate electrode of a p-type MISFET formed on the gate insulation film and having a thickness smaller than that of the silicide gate electrode of the n-type MISFET, the silicide gate electrode of the p-type MISFET having a ratio of metal content higher than that of the silicide gate electrode of the n-type MISFET.
    Type: Application
    Filed: November 17, 2010
    Publication date: March 17, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Tomonori Aoyama