Patents by Inventor Tomonori Sekiguchi
Tomonori Sekiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130057326Abstract: Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.Type: ApplicationFiled: August 29, 2012Publication date: March 7, 2013Inventors: Yoshimitsu YANAGAWA, Tomonori Sekiguchi, Akira Kotabe, Takamasa Suzuki
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Publication number: 20120267792Abstract: A stacked device includes a plurality of semiconductor chips connected to each other by through electrodes. The same number of through electrodes are included in each of paths extending from a first power source terminal through each of circuit elements formed for the semiconductor chips to a second power source terminal.Type: ApplicationFiled: April 25, 2012Publication date: October 25, 2012Applicant: Elpida Memory, Inc.Inventors: Shinichi TAKAYAMA, Kazuo ONO, Tomonori SEKIGUCHI, Akira KOTABE, Yoshimitsu YANAGAWA
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Publication number: 20120249180Abstract: A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the fifth transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter.Type: ApplicationFiled: March 23, 2012Publication date: October 4, 2012Inventors: Takamasa SUZUKI, Akira Kotabe, Tomonori Sekiguchi, Riichiro Takemura
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Publication number: 20120217620Abstract: The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.Type: ApplicationFiled: May 2, 2012Publication date: August 30, 2012Inventors: Makoto SAEN, Kenichi Osada, Masanao Yamaoka, Tomonori Sekiguchi
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Patent number: 8199596Abstract: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.Type: GrantFiled: November 3, 2010Date of Patent: June 12, 2012Assignee: Hitachi, Ltd.Inventors: Satoru Akiyama, Riichiro Takemura, Takayuki Kawahara, Tomonori Sekiguchi
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Publication number: 20120135548Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.Type: ApplicationFiled: February 5, 2012Publication date: May 31, 2012Inventors: SATORU HANZAWA, Hitoshi Kume, Motoyasu Terao, Tomonori Sekiguchi, Makoto Saen
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Patent number: 8184463Abstract: The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.Type: GrantFiled: December 13, 2009Date of Patent: May 22, 2012Assignee: Hitachi, Ltd.Inventors: Makoto Saen, Kenichi Osada, Masanao Yamaoka, Tomonori Sekiguchi
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Publication number: 20120092921Abstract: A technique for increasing rewriting current without increasing a power supply voltage and also reducing location dependency inside a memory array of a resistive state after the rewriting is provided in a resistance change memory in which the resistance value of a memory cell changes between logical values “1” and “0”. In the resistance change memory, bit lines are formed into a layered structure, the bit line select switches for connecting to the global bit line are provided at both ends of the local bit line, and a control method of the bit line select switches is changed in the writing and the reading, thereby realizing the optimum array configurations for each of them. More specifically, in the writing and the reading, two current paths are provided in parallel by turning ON the bit line select switches simultaneously.Type: ApplicationFiled: December 19, 2011Publication date: April 19, 2012Inventors: Kazuo ONO, Riichiro Takemura, Tomonori Sekiguchi
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Patent number: 8134905Abstract: In an information memory apparatus having minute areas for storing information arranged in x, y and z directions three-dimensionally, parallel rays are irradiated to a memory area MA in a direction perpendicular to a z-axis to take projection images of the memory area MA while rotating the memory area MA around the z-axis little by little. The light rays irradiated at this time have a size which covers at least a direction of an x-y plane of the memory area. A computation unit PU finds data and addresses of minute areas distributed three-dimensionally by performing computation based upon the principle of computer tomography on the projection images. As for data writing, a change is given to optical transmissivity or light emission characteristics by irradiating laser light focused by a lens OL placed outside the memory area to a desired minute area and causing heat denaturation within the pertinent minute area.Type: GrantFiled: October 30, 2008Date of Patent: March 13, 2012Assignee: Hitachi, Ltd.Inventors: Takao Watanabe, Toshimichi Shintani, Takeshi Maeda, Akemi Hirotsune, Tomonori Sekiguchi
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Patent number: 8130575Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.Type: GrantFiled: August 11, 2011Date of Patent: March 6, 2012Assignee: Hitachi, Ltd.Inventors: Satoru Hanzawa, Hitoshi Kume, Motoyasu Terao, Tomonori Sekiguchi, Makoto Saen
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Patent number: 8102695Abstract: A technique for increasing rewriting current without increasing a power supply voltage and also reducing location dependency inside a memory array of a resistive state after the rewriting is provided in a resistance change memory in which the resistance value of a memory cell changes between logical values “1” and “0”. In the resistance change memory, bit lines are formed into a layered structure, the bit line select switches for connecting to the global bit line are provided at both ends of the local bit line, and a control method of the bit line select switches is changed in the writing and the reading, thereby realizing the optimum array configurations for each of them. More specifically, in the writing and the reading, two current paths are provided in parallel by turning ON the bit line select switches simultaneously.Type: GrantFiled: April 25, 2009Date of Patent: January 24, 2012Assignee: Hitachi, Ltd.Inventors: Kazuo Ono, Riichiro Takemura, Tomonori Sekiguchi
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Publication number: 20110292709Abstract: A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.Type: ApplicationFiled: May 27, 2011Publication date: December 1, 2011Applicant: ELPIDA MEMORY, INC.Inventors: Shinichi TAKAYAMA, Akira KOTABE, Kiyoo ITOH, Tomonori SEKIGUCHI
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Publication number: 20110292722Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogcnidc material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.Type: ApplicationFiled: August 11, 2011Publication date: December 1, 2011Inventors: SATORU HANZAWA, Hitoshi Kume, Motoyasu Terao, Tomonori Sekiguchi, Makoto Saen
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Publication number: 20110205820Abstract: The semiconductor device comprises first and second memory cells, first and second bit lines connected to the first/second memory cells, first and second amplifiers connected to the second bit line, a local input/output line commonly connected to the first/second amplifiers, first and second local column switches connected between the first/second amplifiers and the local input/output line, a second local column switch connected between the second amplifier and the local input/output line, a column select line, a first global column switch connected between the column select line and the first local column switch and controlling a connection therebetween in response to a first select signal, and a second global column switch connected between the column select line and the second local column switch and controlling a connection therebetween in response to a first select signal.Type: ApplicationFiled: February 23, 2011Publication date: August 25, 2011Inventors: Shinichi Takayama, Kazuhiko Kajigaya, Akira Kotabe, Satoru Akiyama, Tomonori Sekiguchi
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Patent number: 7995405Abstract: A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.Type: GrantFiled: December 14, 2010Date of Patent: August 9, 2011Assignees: Hitachi, Ltd., Elpida Memory, Inc.Inventors: Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Hiroaki Nakaya, Shinichi Miyatake, Yuko Watanabe
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Publication number: 20110176379Abstract: A semiconductor memory device includes: first and second bit lines of an open bit-line system; a sense amplifier that amplifies a potential difference between the first and second bit lines; a pair of first and second local data lines corresponding to the first and second bit lines, respectively; and a write amplifier circuit. The write amplifier circuit changes a potential of the second local data line without changing a potential of the first local data line at a time of writing data for the first bit line, and changes a potential of the first local data line without changing a potential of the second local data line at a time of writing data for the second bit line.Type: ApplicationFiled: January 18, 2011Publication date: July 21, 2011Inventors: Shinichi TAKAYAMA, Akira Kotabe, Kazuo Ono, Tomonori Sekiguchi, Yoshimitsu Yanagawa, Riichiro Takemura
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Publication number: 20110164460Abstract: A semiconductor device includes a delay buffer, and a pipeline control circuit. The pipeline control circuit controls the delay buffer to hold read data from outputting to a read/write bus for each of banks based on a read command to the each bank while the pipeline control circuit controlling the delay buffer to output write data to the read/write bus, when a next command to the each bank is a write command for the write data. The read/write bus is common to the banks.Type: ApplicationFiled: January 3, 2011Publication date: July 7, 2011Applicant: Elpida Memory, Inc.Inventors: Kazuhiko Kajigaya, Tomonori Sekiguchi, Kazuo Ono
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Patent number: 7973582Abstract: Disclosed is a timing control circuit which receives a first clock having a period T1 and a group of second clocks of L different phases (where L is a positive integer) spaced apart from each other at substantially equal intervals and which generates a fine timing signal delayed from the rising edge of the first clock by a delay td of approximately td=m·T1+n·(T2/L), where m and n are non-negative integers. The timing control circuit has a coarse delay circuit and a fine delay circuit. The coarse delay circuit counts the rising edges of the first clock after an activate signal is activated and generates a coarse timing signal delayed from the first clock by approximately m·T1. The fine delay circuit has a circuit which, after the activate signal is activated, detects a second clock, which has a rising edge that immediately follows the rising edge of the first clock, from among the group of L-phase second clocks.Type: GrantFiled: September 5, 2008Date of Patent: July 5, 2011Assignee: Elpida Memory, Inc.Inventors: Akira Ide, Yasuhiro Takai, Tomonori Sekiguchi, Riichiro Takemura, Satoru Akiyama, Hiroaki Nakaya
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Patent number: 7969765Abstract: A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.Type: GrantFiled: October 8, 2008Date of Patent: June 28, 2011Assignee: Elpida Memory, Inc.Inventors: Tomonori Sekiguchi, Shinichi Miyatake, Takeshi Sakata, Riichiro Takemura, Hiromasa Noda, Kazuhiko Kajigaya
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Publication number: 20110134678Abstract: A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing the restore operation by time division. Further, because a parasitic CR model of a first sense amplifier and that of a second sense amplifier become mutually the same, high sensitivity can be maintained.Type: ApplicationFiled: December 3, 2010Publication date: June 9, 2011Applicant: Elpida Memory, Inc.Inventors: Takenori Sato, Kazuhiko Kajigaya, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe, Satoru Akiyama