Patents by Inventor Tomonori Sekiguchi
Tomonori Sekiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110110150Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.Type: ApplicationFiled: January 18, 2011Publication date: May 12, 2011Inventors: SATORU HANZAWA, Hitoshi Kume, Motoyasu Terao, Tomonori Sekiguchi, Makoto Sean
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Publication number: 20110103136Abstract: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.Type: ApplicationFiled: November 3, 2010Publication date: May 5, 2011Inventors: Satoru Akiyama, Riichiro Takemura, Takayuki Kawahara, Tomonori Sekiguchi
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Patent number: 7933141Abstract: In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes.Type: GrantFiled: April 1, 2009Date of Patent: April 26, 2011Assignee: Elpida Memory, Inc.Inventors: Kazuhiko Kajigaya, Soichiro Yoshida, Tomonori Sekiguchi, Riichiro Takemura, Yasutoshi Yamada
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Publication number: 20110079858Abstract: A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.Type: ApplicationFiled: December 14, 2010Publication date: April 7, 2011Inventors: Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Hiroaki Nakaya, Shinichi Miyatake, Yuko Watanabe
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Patent number: 7903492Abstract: Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command.Type: GrantFiled: December 17, 2008Date of Patent: March 8, 2011Assignee: Elpida Memory, Inc.Inventors: Akira Ide, Yasuhiro Takai, Tomonori Sekiguchi, Riichiro Takemura, Satoru Akiyama, Hiroaki Nakaya
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Patent number: 7903449Abstract: A semiconductor memory device (e.g. DRAM) is constituted of a memory cell array including a plurality of memory cells, a plurality of word line drivers, a plurality of sense amplifiers, and a plurality of dummy capacitors. The memory cells, each of which includes a transistor and a capacitor, are positioned at intersections between the word lines and the bit lines. The first electrodes of the capacitors are connected to the transistors in the memory cells. The first electrodes of the dummy capacitors are connected together and are supplied with a second potential (e.g. VDD or VSS). The second electrodes of the dummy capacitors are connected together with the second electrodes of the capacitors of the memory cells and are supplied with a first potential (e.g. VPL). The dummy capacitors serve as smoothing capacitances for the plate voltage VPL so as to reduce plate noise.Type: GrantFiled: June 16, 2009Date of Patent: March 8, 2011Assignee: Elpida Memory, Inc.Inventors: Kazuhiko Kajigaya, Soichiro Yoshida, Tomonori Sekiguchi, Riichiro Takemura, Yasutoshi Yamada
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Publication number: 20110044092Abstract: A resistance variable memory reduces the nonuniformity of resistance values after programming, so that a rewrite operation can be performed on a memory cell at high speed. A reference resistor is connected in series with the resistance variable memory cell, and a sensor amplifier detects whether the potential at an intermediate node between the memory cell and the reference resistor exceeds a given threshold voltage, so as to stop the write operation based on a detection result.Type: ApplicationFiled: October 30, 2010Publication date: February 24, 2011Inventors: KAZUO ONO, Riichiro Takemura, Tomonori Sekiguchi
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Patent number: 7894232Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.Type: GrantFiled: April 21, 2009Date of Patent: February 22, 2011Assignee: Hitachi, Ltd.Inventors: Satoru Hanzawa, Hitoshi Kume, Motoyasu Terao, Tomonori Sekiguchi, Makoto Saen
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Patent number: 7876627Abstract: A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.Type: GrantFiled: January 3, 2008Date of Patent: January 25, 2011Assignees: Hitachi, Ltd., Elpida Memory, Inc.Inventors: Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Hiroaki Nakaya, Shinichi Miyatake, Yuko Watanabe
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Patent number: 7848177Abstract: The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decoder and transfer the signal to the column multiplexer in the post stage subsequent to the Y decoder; and a third latch which can hold an output signal of the sense amplifier and transfer the signal to the output buffer in the post stage subsequent to the sense amplifier. The structure makes it possible to pipeline-control a series of processes for reading data stored in the non-volatile semiconductor memory, and enables low-latency access even with access requests from CPUs conflicting.Type: GrantFiled: November 12, 2008Date of Patent: December 7, 2010Assignee: Renesas Electronics CorporationInventors: Shinya Kajiyama, Yutaka Shinagawa, Makoto Mizuno, Hideo Kasai, Takao Watanabe, Riichiro Takemura, Tomonori Sekiguchi
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Patent number: 7843250Abstract: A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip.Type: GrantFiled: January 13, 2010Date of Patent: November 30, 2010Assignee: Hitachi, Ltd.Inventors: Hiroaki Nakaya, Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura
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Patent number: 7843751Abstract: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.Type: GrantFiled: January 12, 2009Date of Patent: November 30, 2010Assignee: Hitachi, LtdInventors: Satoru Akiyama, Riichiro Takemura, Takayuki Kawahara, Tomonori Sekiguchi
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Patent number: 7835171Abstract: A resistance variable memory reduces the nonuniformity of resistance values after programming, so that a rewrite operation can be performed on a memory cell at high speed. A reference resistor is connected in series with the resistance variable memory cell, and a sensor amplifier detects whether the potential at an intermediate node between the memory cell and the reference resistor exceeds a given threshold voltage, so as to stop the write operation based on a detection result.Type: GrantFiled: July 11, 2008Date of Patent: November 16, 2010Assignee: Hitachi, Ltd.Inventors: Kazuo Ono, Riichiro Takemura, Tomonori Sekiguchi
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Publication number: 20100277996Abstract: A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.Type: ApplicationFiled: February 8, 2008Publication date: November 4, 2010Inventors: Riichiro TAKEMURA, Kiyoo ITOH, Tomonori SEKIGUCHI, Takeshi SAKATA, Katsutaka KIMURA
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Patent number: 7821804Abstract: In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few each of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.Type: GrantFiled: September 6, 2007Date of Patent: October 26, 2010Assignee: Elpida Memory, Inc.Inventors: Tomonori Sekiguchi, Riichiro Takemura, Kazuhiko Kajigaya, Katsutaka Kimura, Tsugio Takahashi
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Patent number: 7809920Abstract: In an information processor including memory devices such as DRAMs and others, by reducing the power consumption of memory devices and efficiently repairing defect bits, a highly reliable information processor is realized. In an information processor including an external memory such as a DRAM, a second memory whose power consumption at the access time is smaller than that of the external memory is disposed, and cache data of the external memory and repair data are stored in this second memory. To an input address given from a central processing unit via a primary cache controller, a memory controller determines a hit or a miss with reference to a tag memory for cache and a tag memory for repair, and when one or both of tag memory for cache and a tag memory for repair are hit, it accesses the second memory.Type: GrantFiled: February 8, 2007Date of Patent: October 5, 2010Assignee: Hitachi, Ltd.Inventors: Takao Watanabe, Motokazu Ozawa, Tomonori Sekiguchi
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Patent number: 7804700Abstract: A semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at the intersections of the plurality of word lines and the plurality of bit lines and each of that includes a MIS transistor and a memory element, a decoder circuit for selecting a plurality of word lines, and a sense-amplifier circuit for determining information that is read from any of the plurality of memory cells to any of the plurality of bit lines, wherein a twist connector for switching the wiring order of the plurality of word lines is provided and level-stabilizing circuits, for supplying the potential level of a non-selected state to the plurality of word lines in the non-selected state are arranged in the area below the twist connector.Type: GrantFiled: December 23, 2008Date of Patent: September 28, 2010Assignee: Elpida Memory, Inc.Inventors: Yasutoshi Yamada, Tomonori Sekiguchi, Riichiro Takemura, Kazuhiko Kajigaya
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Patent number: 7772911Abstract: Disclosed is a timing control circuit that receives a first clock having a period T1, a group of second clocks of L different phases spaced apart from each other at substantially equal intervals and selection signals m, n supplied thereto and generates a fine timing signal delayed from the rising edge of the first clock signal by a delay td of approximately td=m·T1+n·(T2/L). The timing control circuit includes a coarse delay circuit and a fine delay circuit. The coarse delay circuit includes a counter for counting a rising edge of the first clock signal after an activate signal is activated and generates a coarse timing signal whose amount of delay from the first clock signal is approximately m·T1.Type: GrantFiled: September 11, 2008Date of Patent: August 10, 2010Assignee: Elpida Memory, Inc.Inventors: Akira Ide, Yasuhiro Takai, Tomonori Sekiguchi, Riichiro Takemura, Satoru Akiyama, Hiroaki Nakaya
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Patent number: 7750712Abstract: A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.Type: GrantFiled: December 5, 2008Date of Patent: July 6, 2010Assignee: Elpida Memory, Inc.Inventors: Akira Ide, Yasuhiro Takai, Akira Kotabe, Tomonori Sekiguchi, Riichiro Takemura, Satoru Akiyama
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Publication number: 20100155921Abstract: The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.Type: ApplicationFiled: December 13, 2009Publication date: June 24, 2010Inventors: Makoto SAEN, Kenichi Osada, Masanao Yamaoka, Tomonori Sekiguchi