Abstract: Measuring current-voltage (I-V) characteristics of a solar cell using a lamp that emits light, a substrate that includes a plurality of solar cells, a positive electrode attached to the solar cells, and a negative electrode peripherally deposited around each of the solar cells and connected to a common ground, an articulation platform coupled to the substrate, a multi-probe switching matrix or a Z-stage device, a programmable switch box coupled to the multi-probe switching matrix or Z-stage device and selectively articulating the probes by raising the probes until in contact with at least one of the positive electrode and the negative electrode and lowering the probes until contact is lost with at least one of the positive electrode and the negative electrode, a source meter coupled to the programmable switch box and measuring the I-V characteristics of the substrate.

Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.

Abstract: Forming a resistive memory structure at a temperature well above the operating temperature can reduce the forming voltage and create a defect distribution with higher stability and lower programming voltages. The forming temperature can be up to 200 C above the operating temperature. The memory chip can include an embedded heater in the chip package, allowing for a chip forming process after packaging.

Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract: In one aspect of the invention, a process chamber is provided. The chamber includes a plurality of sputter guns with a target affixed to one end of each of the sputter guns. Each of the plurality of sputter guns is coupled to a first power source. The first power source is operable to provide a pulsed power supply to each of the plurality of sputter guns. The pulsed power supply has a duty cycle that is less than 30%. A substrate support disposed at a distance from the plurality of sputter guns is included. The substrate support is coupled to a second power source. The second power source is operable to bias a substrate disposed on the substrate support, wherein the duty cycle of the second power source is synchronized with a duty cycle of the first power source. A method of performing a deposition process is also included.

Abstract: A multi-zone, combinatorial, single wafer showerhead is used to concurrently develop hardware, materials, unit processes, and unit process sequences. The multi-zone, combinatorial, single wafer showerhead utilizes showerhead pucks to perform process sequences on isolated regions of a single substrate. The showerhead pucks are designed so that they are easily interchangeable to allow the characterization of the interaction between hardware characteristics, process parameters, and their influence on the result of the process sequence.

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

Abstract: Resistive switching memory elements are provided that may contain electroless metal electrodes and metal oxides formed from electroless metal. The resistive switching memory elements may exhibit bistability and may be used in high-density multi-layer memory integrated circuits. Electroless conductive materials such as nickel-based materials may be selectively deposited on a conductor on a silicon wafer or other suitable substrate. The electroless conductive materials can be oxidized to form a metal oxide for a resistive switching memory element. Multiple layers of conductive materials can be deposited each of which has a different oxidation rate. The differential oxidization rates of the conductive layers can be exploited to ensure that metal oxide layers of desired thicknesses are formed during fabrication.

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract: A resistive-switching memory element is described. The memory element includes a first electrode, a porous layer over the first electrode including a point defect embedded in a plurality of pores of the porous layer, and a second electrode over the porous layer, wherein the nonvolatile memory element is configured to switch between a high resistive state and a low resistive state.

Abstract: Non linear current response circuits can be used in embedded resistive memory cell for reducing power consumption, together with improving reliability of the memory array. The non linear current response circuits can include two back to back leaky PIN diodes, two parallel anti-directional PIN diodes, two back to back Zener-type metal oxide diodes, or ovonic switching elements, along with current limiting resistor for standby power reduction at the low voltage region. Also, the proposed embedded ReRAM implementation methods based upon 1T2D1R scheme can be integrated into the advanced FEOL process technologies including vertical pillar transistor and/or 3D fin-shaped field effect transistor (FinFET) for realizing a highly compact cell density.

Abstract: Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm2) measured at 0.5 volts (V) per twenty angstroms of the thickness of the metal oxide.

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies.

Abstract: An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

Abstract: A method and system includes a first substrate and a second substrate, each substrate comprising a predetermined baseline transmittance value at a predetermine wavelength of light, processing regions on the first substrate by combinatorially varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production, performing a first characterization test on the processed regions on the first substrate to generate first results, processing regions on a second substrate in a combinatorial manner by varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production based on the first results of the first characterization test, performing a second characterization test on the processed regions on the second substrate to generate second results, and determining whether at least one of the first substrate and the second substrate meet a predetermined quality threshold based on the second res

Abstract: Simultaneous measurement of an internal quantum efficiency and an external quantum efficiency of a solar cell using an emitter that emits light; a three-way beam splitter that splits the light into solar cell light and reference light, wherein the solar cell light strikes the solar cell; a reference detector that detects the reference light; a reflectance detector that detects reflectance light, wherein the reflectance light comprises a portion of the solar cell light reflected off the solar cell; a source meter operatively coupled to the solar cell; a multiplexer operatively coupled to the solar cell, the reference detector, and the reflectance detector; and a computing device that simultaneously computes the internal quantum efficiency and the external quantum efficiency of the solar cell.

Abstract: In some embodiments, apparatus are provided that provide for flexible processing in high productivity combinatorial (HPC) system. The apparatus allow for interchangeable functionality that includes deposition, plasma treatment, ion beam treatment, in-situ annealing, and in-situ metrology. The apparatus are designed so that the functionality may be integrated within a single processing chamber for enhanced flexibility.

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract: Embodiments described herein provide systems and methods for performing vapor deposition processes on substrates. A housing defining a processing chamber is provided. A substrate support is positioned within the processing chamber and configured to support a substrate. A fluid supply system including a plurality precursor sources is included. A fluid conduit assembly is coupled to the fluid supply system and configurable to selectively expose a first site-isolated region defined on the substrate to the respective precursors of a first and a second of the plurality of precursor sources and selectively expose a second site-isolated region defined on the substrate to the respective precursors of a third and a fourth of the plurality of precursor sources.