Abstract: The present invention relates to a memory system including an external clock and a memory chip connected to the external clock. The external clock generates an operating signal at an operating frequency that controls at least one electrical component of the memory system. The memory chip includes a frequency detector that detects at least a range of frequency values for the operating frequency. Further, the frequency detector includes a reference frequency generator that generates a reference signal at a reference frequency.

Abstract: A receiver for use in a device such as a memory device is provided. The receiver circuit is located on the same integrated circuit as a temperature sensor (or other sensor). A data receiver and strobe receiver are coupled to the temperature sensor. A flip-flop receives a data input from the data receiver and this data input is latched based upon the strobe receiver. In the preferred embodiment, the timing of these inputs is controlled, at least in part, by the temperature sensor output.

Abstract: A random access memory comprises a plurality of data pads and an array of memory cells comprising a first portion of memory cells and a second portion of memory cells. The random access memory comprises a first line configured to receive first data signals between the first portion of memory cells and the data pads and a second line configured to receive second data signals between the second portion of memory cells and the data pads. The first portion of memory cells is configured to be made inaccessible to eliminate the first data signals and a first number of the data pads and the second portion of memory cells is configured to be made inaccessible to eliminate the second data signals and a second number of the data pads.

Abstract: The present invention relates to a method of operating a memory system comprising a memory chip. An operating signal is generated at an operating frequency. The operating frequency is applied to the memory chip to control one or more electrical components of the memory system. A reference signal is generated at a reference frequency within the memory chip and a range of values for the operating frequency is detected based on the reference signal and the operating signal.

Abstract: An output circuit (OUT) can be activated via an activation input (AKT), in the activated state starts an output process for data (D) to be read out, in synchronism with the first internal clock (CLKI1), and outputs the data (D) with a specific phase shift (?TOUT) with respect to the first internal clock (CLKI1), in synchronism with the external clock (CLKE), at a data connection (P). A counting unit (CT) starts a counting process for recording the number of successively following first levels of the first internal clock (CLKI1) as soon as a second internal clock (CLKI2), which is synchronized to the external clock (CLKE), for the first time assumes a first level while an output control signal (PAR) is at first level. It activates the output circuit (OUT) as soon as the number of successively following first levels of the first internal clock (CLKI1) has reached a predetermined value.

Abstract: A random access memory comprises a plurality of data pads and an array of memory cells comprising a first portion of memory cells and a second portion of memory cells. The random access memory comprises a first line configured to receive first data signals between the first portion of memory cells and the data pads and a second line configured to receive second data signals between the second portion of memory cells and the data pads. The first portion of memory cells is configured to be made inaccessible to eliminate the first data signals and a first number of the data pads and the second portion of memory cells is configured to be made inaccessible to eliminate the second data signals and a second number of the data pads.

Abstract: The present invention relates to a method of operating a memory system comprising a memory chip. An operating signal is generated at an operating frequency. The operating frequency is applied to the memory chip to control one or more electrical components of the memory system. A reference signal is generated at a reference frequency within the memory chip and a range of values for the operating frequency is detected based on the reference signal and the operating signal.

Abstract: A random access memory comprises an array of memory cells, a memory configured to receive data from the array of memory cells, a bypass circuit configured to receive the data from the array of memory cells and to bypass the memory, and a circuit configured to select between receiving the data from the memory to provide first output signals and receiving the data from the bypass circuit to provide second output signals based on a column address strobe latency signal.

Abstract: A random access memory comprises a first circuit configured to receive a strobe signal and provide pulses in response to transitions in the strobe signal. The random access memory comprises a second circuit configured to receive the strobe signal to latch data into the second circuit, and to receive the pulses to latch the latched data into the second circuit after the transitions in the strobe signal.

Abstract: A method of protecting an integrated circuit that includes sensing a temperature of an integrated circuit, comparing the sensed temperature with a threshold temperature and controlling operation of the integrated circuit based on the comparing.

Abstract: A method of throttling the frequency with which an integrated circuit is accessed includes sensing the temperature of the integrated circuit die and converting the sensed temperature to a digital signal. The digital signal is stored in a register of the integrated circuit. The digital signal is read, and the frequency with which the integrated circuit is accessed is adjusted dependent at least in part upon the temperature of the die as indicated by the digital signal.

Abstract: A method of protecting an integrated circuit that includes sensing a temperature of an integrated circuit that has a data pin, generating a temperature data signal based on the sensing, implementing a temperature sensing protocol and supplying the temperature data signal to the data pin based on the temperature sensing protocol.

Abstract: A switching network with trimmable resistors lies in a control loop of a voltage generator that can be switched off from the supply voltage by a logic device. The logic device and also the switching network are driven by the same signals. The circuit configuration can be used for trimming or switching off the output voltage generated by the voltage generator during the functional test. As many settings as possible for the output voltage can be tested by a small number of control signals.

Abstract: A delay lock loop circuit includes a forward delay circuit receiving a reference clock signal and issuing a first delayed clock signal. The forward delay circuit adjustably shifts in time the first delayed clock signal relative to the reference clock signal. A fixed delay circuit receives the first delayed clock signal and issues a second delayed clock signal. A feedback delay circuit receives a selected one of the first delayed and the second delayed clock signals, and issues a feedback clock signal. The feedback clock signal is shifted in time relative to the selected one of the first delayed and the second delayed clock signals.

Abstract: A circuit and method for suppressing the effect of noise on a data strobe signal DQS in a double data rate (DDR) SDRAM is provided. The circuit includes a data input latch circuit for receiving data to be stored and for latching the data in a memory array in response to a control signal; and a control signal generator for generating the control signal in response to a data strobe signal wherein the control signal has a predetermined minimum pulse width of the data strobe signal. The control signal generator includes a reset/set flip-flop for generating the control signal, wherein the flip-flop is set by the data strobe signal; and a low pass filter for receiving the data strobe signal and for outputting a reset signal to the flip-flop if the data strobe signal is greater than the predetermined minimum pulse width.

Abstract: A method of operating a memory system that includes generating an operating signal, controlling one or more electrical components with the operating signal and having a memory chip detect at the least a range of values for the operating frequency.

Abstract: A method of using a memory chip that includes operating a memory chip of a memory system and sending a command signal to the memory chip, wherein the command signal contains information regarding an operational frequency of a system clock signal of the memory system.

Abstract: A method of self-repair for a DRAM integrated circuit includes internally generating a bit pattern and writing the pattern to an array of memory cells within the integrated circuit. The DRAM integrated circuit reads from the array and internally compares the read data with the generated pattern to determine addresses for failed memory cells. The DRAM integrated circuit sets internal soft fuses that record the addresses of the failed memory cells and provide substitute memory cells for the failed memory cells from a redundant memory portion of the array. The self-repair process occurs each time the DRAM integrated circuit is powered up, thus permitting the integrated circuit to adapt to failures when installed in electronic devices and lessening the need for repair during manufacturing.

Abstract: A circuit and method for suppressing the effect of noise on a data strobe signal DQS in a double data rate (DDR) SDRAM is provided. The circuit includes a data input latch circuit for receiving data to be stored and for latching the data in a memory array in response to a control signal; and a control signal generator for generating the control signal in response to a data strobe signal wherein the control signal has a predetermined minimum pulse width of the data strobe signal. The control signal generator includes a reset/set flip-flop for generating the control signal, wherein the flip-flop is set by the data strobe signal; and a low pass filter for receiving the data strobe signal and for outputting a reset signal to the flip-flop if the data strobe signal is greater than the predetermined minimum pulse width.

Abstract: A method of using a memory chip includes operating a memory chip of a memory system and sending a command signal to the memory chip, wherein the command signal contains information regarding an operational frequency of a system clock signal of the memory system. The method provides the advantage of enabling high operation frequencies and thus increasing the SDRAM internal timing margin.