Patents by Inventor Toru Maeda

Toru Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210257329
    Abstract: Provided is a mounting device in which two or more semiconductor chips are laminated and mounted at a plurality of locations on a substrate, said mounting device including: a stage that supports the substrate; a bonding part that laminates and mounts the plurality of semiconductor chips on the substrate while heating the plurality of semiconductor chips and the substrate; and a heat insulating member that is interposed between the stage and the substrate, said heat insulating member including a first layer which is in contact with the substrate and to which heat is applied from the bonding part via the semiconductor chips and the substrate, and a second layer which is disposed closer to the stage side than the first layer, wherein the first layer has a larger heat resistance than the second layer.
    Type: Application
    Filed: September 29, 2017
    Publication date: August 19, 2021
    Applicant: SHINKAWA LTD.
    Inventors: Tomonori NAKAMURA, Toru MAEDA
  • Patent number: 11094567
    Abstract: A mounting apparatus for manufacturing a semiconductor device by bonding a semiconductor chip (12) to a mounted object that is a substrate (30) or another semiconductor chip (12) is provided. The mounting apparatus includes: a stage (120) on which the substrate (30) is placed, a mounting head (124) that is capable of moving relative to the stage (120) and bonds the semiconductor chip (12) to the mounted object, and an irradiation unit (108 that irradiates, from a lower side of the stage (120), an electromagnetic wave transmitting through the stage and heating the substrate (30). The stage (120) has a first layer (122) formed on an upper surface side, and the first layer (122) has a greater thermal resistance in a plane direction than the thermal resistance in a thickness direction.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 17, 2021
    Assignee: SHINKAWA LTD.
    Inventors: Tomonori Nakamura, Toru Maeda, Tetsuo Takano
  • Publication number: 20210251112
    Abstract: A semiconductor mounting device for mounting chip components on a substrate, wherein the device is reduced in size. A semiconductor mounting device 10 comprises: a temporary placement stage 12 on which are loaded a plurality of chip components 30a, 30b, 30c; a conveyance head 14 that conveys the chip components 30a, 30b, 30c to the temporary placement stage 12, and also loads each of the chip components 30a, 30b, 30c on the temporary placement stage 12 so that the relative positions of the plurality of chip components 30a, 30b, 30c reach predetermined positions; a mounting stage 16 that secures a substrate 36 by suction; and a mounting head 18 that suctions the plurality of chip components 30a, 30b, 30c loaded on the temporary placement stage 12, and pressurizes while keeping the relative positions at prescribed positions on the substrate 36 that is secured by suction to the mounting stage 16.
    Type: Application
    Filed: September 19, 2018
    Publication date: August 12, 2021
    Applicant: SHINKAWA LTD.
    Inventors: Tomonori NAKAMURA, Toru MAEDA
  • Patent number: 11024596
    Abstract: [Problem] To bond an electronic component on a substrate via an adhesive material satisfactorily. [Solution] A bonding device 10 for thermally bonding an electronic component 100 to a substrate 110 or to another electronic component via an adhesive material 112, the bonding device being provided with: a bonding tool 40 comprising a bonding distal-end portion 42 which includes a bonding surface 44 and tapered side surfaces 46 formed in a tapering shape becoming narrower toward the bonding surface 44, the bonding surface 44 having a first suction hole 50 for suction-attaching the electronic component 100 via an individual piece of a porous sheet 130, the tapered side surfaces 46 having second suction holes 52, 54 for suction-attaching the porous sheet 130; and a bonding control unit 30 which controls the first suction hole 50 and the second suction holes 52, 54 independently from each other.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 1, 2021
    Assignee: SHINKAWA LTD.
    Inventors: Osamu Watanabe, Tomonori Nakamura, Toru Maeda, Satoru Nagai, Yuichiro Noguchi
  • Patent number: 10896901
    Abstract: The disclosure is provided with: a temporary crimping step in which one or more semiconductor chips 10 are sequentially laminated while being temporarily crimped in each of two or more locations on a substrate 30 to thereby form chip stacks ST in a temporarily crimped state; and a permanent crimping step in which the top surfaces of all of the chip stacks ST formed in the temporarily crimped state are sequentially heated, pressurized, and permanently crimped. Furthermore, a specifying step is provided prior to the temporary crimping step for specifying a separation distance Dd which is the distance from the chip stacks ST under permanent crimping to a location at which the temperature of the substrate 30, the temperature having been raised by heating for the permanent crimping, becomes less than or equal to a prescribed permissible temperature Td, and in the temporary crimping step, the chip stacks ST in the temporarily crimped state are formed separated from each other by the separation distance Dd or more.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: January 19, 2021
    Assignee: SHINKAWA LTD.
    Inventors: Tomonori Nakamura, Toru Maeda
  • Publication number: 20210005570
    Abstract: [Problem] To bond an electronic component on a substrate via an adhesive material satisfactorily. [Solution] A bonding device 10 for thermally bonding an electronic component 100 to a substrate 110 or to another electronic component via an adhesive material 112, the bonding device being provided with: a bonding tool 40 comprising a bonding distal-end portion 42 which includes a bonding surface 44 and tapered side surfaces 46 formed in a tapering shape becoming narrower toward the bonding surface 44, the bonding surface 44 having a first suction hole 50 for suction-attaching the electronic component 100 via an individual piece of a porous sheet 130, the tapered side surfaces 46 having second suction holes 52, 54 for suction-attaching the porous sheet 130; and a bonding control unit 30 which controls the first suction hole 50 and the second suction holes 52, 54 independently from each other.
    Type: Application
    Filed: November 29, 2017
    Publication date: January 7, 2021
    Applicant: SHINKAWA LTD.
    Inventors: Osamu WATANABE, Tomonori NAKAMURA, Toru MAEDA, Satoru NAGAI, Yuichiro NOGUCHI
  • Patent number: 10847434
    Abstract: A method of manufacturing a semiconductor device in which a prescribed target lamination number of semiconductor chips are laminated on a substrate, the method includes: a first lamination step of laminating while temporarily bonding one or more semiconductor chips on the substrate to thereby form a first chip laminate body; a first permanent bonding step of pressurizing while heating from the upper side of the first chip laminate body to thereby collectively and permanently bond the one or more semiconductor chips; a second lamination step of sequentially laminating while temporarily bonding two or more semiconductor chips on the permanently bonded semiconductor chips to thereby form a second chip laminate body; and a second permanent bonding step of pressurizing while heating from the upper side of the second chip laminate body to thereby collectively permanently bond the two or more semiconductor chips.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 24, 2020
    Assignee: SHINKAWA LTD.
    Inventors: Tomonori Nakamura, Toru Maeda
  • Publication number: 20200362441
    Abstract: An aluminum alloy wire with a composition that contains at least one metallic element selected from the group consisting of Fe, Cr, Ni, Co, Ti, Sc, Zr, Nb, Hf, and Ta in the total amount of more than 1.4 atomic percent and 5.1 atomic percent or less and a remainder of Al and incidental impurities, wherein the aluminum alloy wire has a tensile strength of 250 MPa or more and an electrical conductivity of 50% IACS or more.
    Type: Application
    Filed: December 21, 2018
    Publication date: November 19, 2020
    Inventors: Toru MAEDA, Tetsuya KUWABARA, Akiko INOUE, Hiroyuki OGIWARA
  • Publication number: 20200286854
    Abstract: Provided is a method for setting the conditions for heating a semiconductor chip during bonding of the semiconductor chip using an NCF, wherein a heating start temperature and a rate of temperature increase are set on the basis of a viscosity characteristic map that indicates changes in viscosity with respect to temperature of the NCF at various rates of temperature increase and a heating start temperature characteristic map that indicates changes in viscosity with respect to temperature of the NCF when the heating start temperature is changed at the same rate of temperature increase.
    Type: Application
    Filed: September 14, 2018
    Publication date: September 10, 2020
    Applicant: SHINKAWA LTD.
    Inventors: Tomonori NAKAMURA, Toru MAEDA, Satoru NAGAI, Yoshihiro SAEKI, Osamu WATANABE
  • Publication number: 20200243356
    Abstract: A mounting apparatus for manufacturing a semiconductor device by bonding a semiconductor chip (12) to a mounted object that is a substrate (30) or another semiconductor chip (12) is provided. The mounting apparatus includes: a stage (120) on which the substrate (30) is placed, a mounting head (124) that is capable of moving relative to the stage (120) and bonds the semiconductor chip (12) to the mounted object, and an irradiation unit (108 that irradiates, from a lower side of the stage (120), an electromagnetic wave transmitting through the stage and heating the substrate (30). The stage (120) has a first layer (122) formed on an upper surface side, and the first layer (122) has a greater thermal resistance in a plane direction than the thermal resistance in a thickness direction.
    Type: Application
    Filed: May 29, 2018
    Publication date: July 30, 2020
    Applicant: SHINKAWA LTD.
    Inventors: Tomonori NAKAMURA, Toru MAEDA, Tetsuo TAKANO
  • Publication number: 20200235070
    Abstract: A mounting apparatus for stacking and mounting two or more semiconductor chips at a plurality of locations on a substrate includes: a first mounting head for forming, at a plurality of locations on the substrate, temporarily stacked bodies in which two or more semiconductor chips are stacked in a temporarily press-attached state; and a second mounting head for forming chip stacked bodies by sequentially finally press-attaching the temporarily stacked bodies formed at the plurality of locations. The second mounting head includes: a press-attaching tool for heating and pressing an upper surface of a target temporarily stacked body to thereby finally press-attach the two or more semiconductor chips configuring the temporarily stacked body altogether; and one or more heat-dissipation tools having a heat-dissipating body which, by coming into contact with an upper surface of another stacked body positioned around the target temporarily stacked body, dissipates heat from the another stacked body.
    Type: Application
    Filed: January 30, 2018
    Publication date: July 23, 2020
    Applicant: SHINKAWA LTD.
    Inventors: Tomonori NAKAMURA, Toru MAEDA
  • Patent number: 10487546
    Abstract: This door locking device for a vehicle includes: an electronic key and an in-vehicle device. The electronic key stores a first threshold defining an extension of a first region in which an electric field intensity of a response request signal is strong and a second threshold for defining an extension of a second region in which an electric field intensity is weaker than the first region around the first region. The electronic key outputs, based on the electric field intensity of the response request signal and the first and second thresholds, a response signal including position information indicating whether the electronic key is in the first region, or is outside the first region but in the second region, or is outside the second region. Based on the received response signal, the in-vehicle device switches the door to an unlocked state or a locked state.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: November 26, 2019
    Assignee: KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO
    Inventors: Tetsuya Egawa, Toru Maeda
  • Publication number: 20190316387
    Abstract: This door locking device for a vehicle includes: an electronic key and an in-vehicle device. The electronic key stores a first threshold defining an extension of a first region in which an electric field intensity of a response request signal is strong and a second threshold for defining an extension of a second region in which an electric field intensity is weaker than the first region around the first region. The electronic key outputs, based on the electric field intensity of the response request signal and the first and second thresholds, a response signal including position information indicating whether the electronic key is in the first region, or is outside the first region but in the second region, or is outside the second region. Based on the received response signal, the in-vehicle device switches the door to an unlocked state or a locked state.
    Type: Application
    Filed: January 18, 2017
    Publication date: October 17, 2019
    Applicant: KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHO
    Inventors: Tetsuya EGAWA, Toru MAEDA
  • Publication number: 20190311964
    Abstract: A method of manufacturing a semiconductor device in which a prescribed target lamination number of semiconductor chips are laminated on a substrate, the method includes: a first lamination step of laminating while temporarily bonding one or more semiconductor chips on the substrate to thereby form a first chip laminate body; a first permanent bonding step of pressurizing while heating from the upper side of the first chip laminate body to thereby collectively and permanently bond the one or more semiconductor chips; a second lamination step of sequentially laminating while temporarily bonding two or more semiconductor chips on the permanently bonded semiconductor chips to thereby form a second chip laminate body; and a second permanent bonding step of pressurizing while heating from the upper side of the second chip laminate body to thereby collectively permanently bond the two or more semiconductor chips.
    Type: Application
    Filed: September 29, 2017
    Publication date: October 10, 2019
    Applicant: SHINKAWA LTD.
    Inventors: Tomonori NAKAMURA, Toru MAEDA
  • Publication number: 20190312020
    Abstract: The disclosure is provided with: a temporary crimping step in which one or more semiconductor chips 10 are sequentially laminated while being temporarily crimped in each of two or more locations on a substrate 30 to thereby form chip stacks ST in a temporarily crimped state; and a permanent crimping step in which the top surfaces of all of the chip stacks ST formed in the temporarily crimped state are sequentially heated, pressurized, and permanently crimped. Furthermore, a specifying step is provided prior to the temporary crimping step for specifying a separation distance Dd which is the distance from the chip stacks ST under permanent crimping to a location at which the temperature of the substrate 30, the temperature having been raised by heating for the permanent crimping, becomes less than or equal to a prescribed permissible temperature Td, and in the temporary crimping step, the chip stacks ST in the temporarily crimped state are formed separated from each other by the separation distance Dd or more.
    Type: Application
    Filed: September 28, 2017
    Publication date: October 10, 2019
    Applicant: SHINKAWA LTD.
    Inventors: Tomonori NAKAMURA, Toru MAEDA
  • Publication number: 20190104195
    Abstract: A computer system comprises a first computer having a first processing performed processing by using a storage region; a second computer having a second processing unit provided the storage region, manage a first port for communication with the first processing unit, and execute a processing request to the storage region; and a third computer having a third processing unit manage a second port for communication with the first processing unit. The third processing unit holds port management information for managing a correspondence relationship of the first port and the second port, selects the first port for redirecting on the basis of the port management information in a case of receiving a connection request; and transmits a response notifying the first port for redirecting to the first processing unit.
    Type: Application
    Filed: September 11, 2018
    Publication date: April 4, 2019
    Applicant: HITACHI, LTD.
    Inventors: Taisuke FUKUYAMA, Shuuhei MATSUMOTO, Kyosuke ACHIWA, Toru MAEDA, Hiroto EBARA
  • Publication number: 20180342338
    Abstract: A rare-earth magnet containing Sm, Fe, and N contains an Me and B serving as additive elements, the Me representing at least one element selected from elements in groups 4, 5, and 6 of the periodic table, and a nanocomposite microstructure including an Fe phase, a SmFeN phase, and an MeB phase, in which the SmFeN phase includes at least a Sm2Fe17Nx phase selected from the Sm2Fe17Nx phase and a SmFe9Ny phase, the volume percentage of the SmFe9Ny phase in the microstructure is 65% or less by volume, the atomic percentage of the total content of the Me and B is 0.1 at % or more and 5.0 at % or less with respect to the total amount of Sm, Fe, the Me, and B, and the atomic percentage of Fe in all phases of compounds each containing at least one of the Me and B is 20 at % or less.
    Type: Application
    Filed: November 23, 2016
    Publication date: November 29, 2018
    Inventors: Shigeki Egashira, Kazunari Shimauchi, Toru Maeda
  • Publication number: 20180330853
    Abstract: A method for producing a rare-earth magnet includes a provision step of providing a Sm—Fe-based alloy containing a SmFe9+? phase serving as a main phase by rapidly cooling a molten alloy containing Sm and Fe in an atomic ratio of 1:8.75 to 1:12, a hydrogenation-disproportionation step of subjecting the Sm—Fe-based alloy to hydrogenation-disproportionation treatment to allow part of the SmFe9+? phase (?=0.1 to 3.
    Type: Application
    Filed: November 14, 2016
    Publication date: November 15, 2018
    Inventors: Shigeki Egashira, Kazunari Shimauchi, Toru Maeda
  • Publication number: 20170316856
    Abstract: There is provided a compact for a magnet which can produce a magnetic member having high coercive force. The compact for a magnet is produced by compression-molding a rare earth-iron-based alloy powder containing a plurality of particles of a rare earth-iron-based alloy containing a rare earth element and iron, wherein the rare earth-iron-based alloy satisfies configurations (a) to (c) below and has 5% by volume or more and 20% by volume or less of voids formed therein. (a) Having a structure containing 10% by mass or more and 30% by mass or less of Sm, 10% by mass or less of Mn, and the balance consisting of Fe and inevitable impurities. (b) A composition, Sm2MNxFe17-x (x=0.1 or more and 2.5 or less). (c) An average crystal grain diameter of 700 nm or less.
    Type: Application
    Filed: November 2, 2015
    Publication date: November 2, 2017
    Inventors: Kazunari Shimauchi, Toru Maeda, Motoi Nagasawa
  • Patent number: 9575855
    Abstract: A storage apparatus has a redundant configuration equipped with a plurality of components and includes a first controller and second controller, wherein the first controller is provided with a first processor and a third processor for monitoring the first controller; wherein the second controller is provided with a second processor and a fourth processor for monitoring the second controller; wherein the first processor and the second processor are connected via a first path and the third processor and the fourth processor are connected via a second path; and wherein if a failure occurs at the first controller, the second processor blocks the first path, acquires failure information including a failure location of the first controller via the third processor, the fourth processor, and the second path, executes first failure location identifying processing, and notifies a management terminal of the failure location.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 21, 2017
    Assignee: HITACHI, LTD.
    Inventors: Toru Maeda, Ryosuke Matsubara