Abstract: According to an embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a memory film, a first structure body, and a first connection portion. The stacked body includes a first conductive layer and a second conductive layer. The semiconductor pillar extends in the first direction through the stacked body. The memory film provides between the stacked body and the semiconductor pillar. The first conductive layer includes a first region and a second region. The first region does not overlap the second conductive layer in the first direction. The second region overlaps the second conductive layer in the first direction. The first structure body extends in the first direction through the first region to a position of a front surface of the first region. The first connection portion is electrically connected to the first conductive layer.

Abstract: According to an embodiment, a semiconductor memory device comprises a first region, a second region, and a third region. The first region includes: a part of a stacked body that includes a plurality of conductive layers; and a memory columnar body which has its side surface covered by the stacked body and configures a memory string. The second region includes: a contact; a contact portion connected to the contact, of the conductive layer; and a plurality of first columnar bodies. The third region includes a second columnar body. In a plane parallel to the substrate, a total area of the second columnar body in a small region that has the same area as one or more contact portions, in the third region is larger than a total area of the first columnar body in the one or more contact portions.

Abstract: The memory cell array includes a memory string and a select transistor. The memory string includes plural memory cells connected in series, the memory string being formed to extend in a first direction as a lengthwise direction. The select transistor is connected to one end of the memory string. In the wiring section, a conductive layer and an interlayer insulating layer are laminated alternately to form plural layers. The conductive layer functions as a gate electrode of the memory cells and the select transistor. One select transistor includes plural conductive layers, and the plural conductive layers are connected in common by a common first contact. The plurality of the conductive layers and the first contact include a barrier metal formed in a periphery thereof. The plurality of the conductive layers and the first contact are in contact without the barrier metal therebetween at a boundary thereof.

Abstract: A method for forming a pattern in a conductive layer includes forming the conductive layer on an insulating layer, forming an etching mask on the conductive layer, and selectively etching the conductive layer to reach the insulating layer by using the etching mask. The etching mask includes a first portion masking a first area of the conductive layer, a second portion masking a second area that surrounds the first area via at least one opening that defines a boundary between the first portion and the second portion. The etching mask also includes a first communication portion connecting the first portion and the second portion. The at least one opening includes overlapping portions, and the first communication portion is provided between the overlapping portions.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.

Abstract: A wire harness includes a wire bundle and a sheathing member covering the wire bundle and configured from a nonwoven member that has been hot-pressed. The sheathing member includes a plurality of path regulators along each of an extension direction and a circumference direction of the wire bundle, the path regulators being capable of regulating a path of a long member to be arranged along a surface of the sheathing member.

Abstract: A wire harness includes a wire bundle, an elongated object, and a covering member. The covering member is made of a single sheet-shaped nonwoven member and covers the wire bundle and the elongated object. The covering member includes a first portion that is wound around the wire bundle and is hot-pressed, and a second portion that is continuous with the first portion and that covers the elongated object on the first portion.

Abstract: The memory cell array includes a memory string and a select transistor. The memory string includes plural memory cells connected in series, the memory string being formed to extend in a first direction as a lengthwise direction. The select transistor is connected to one end of the memory string. In the wiring section, a conductive layer and an interlayer insulating layer are laminated alternately to form plural layers. The conductive layer functions as a gate electrode of the memory cells and the select transistor. One select transistor includes plural conductive layers, and the plural conductive layers are connected in common by a common first contact. The plurality of the conductive layers and the first contact include a barrier metal formed in a periphery thereof. The plurality of the conductive layers and the first contact are in contact without the barrier metal therebetween at a boundary thereof.

Abstract: According to one embodiment, a semiconductor memory device includes a source layer; a stacked body; a columnar section; and a contact section extending in the stacking direction and piercing through the stacked body and connected to the source layer. The columnar section including: a channel body extending in the stacking direction and including a lower end, the lower end projecting into the source layer; and a charge storage film provided between the channel body and each of the electrode layers. The source layer including: a first film including metal; and a second film having electric conductivity provided between the first film and the lower end of the channel body, the second film being in contact with the lower end and covering the lower end.

Abstract: An information processing apparatus that includes a plurality of communicating units, and that is capable of performing at least one function, includes an identifying unit and a processing unit. The identifying unit identifies the communicating unit connected to an external device. The processing unit performs processing corresponding to the communicating unit identified by the identifying unit, by using correspondence information that indicates correspondence between the communicating unit and regulation information.

Abstract: According to one embodiment, a non-volatile memory device includes a base layer, a first stacked unit and a second stacked unit disposed above the base layer and arranged in parallel to each other and spaced apart from each other in a first direction, in a plane parallel to the base layer, a first semiconductor layer penetrating the first stacked unit, a second semiconductor layer penetrating in the second stacked unit, the first memory film disposed between the first semiconductor layer and the first stacked unit, and a connecting portion disposed between the base layer and the first stacked unit and between the base layer and the second stacked unit and electrically connecting the first semiconductor layer and the second semiconductor layer. An end portion of the first semiconductor layer is positioned between the connecting portion and the base layer.

Abstract: A method of controlling user information for an information processing apparatus includes the steps of a process of an application program requesting user information controlling unit to obtain an item of said user information, and said user information controlling unit providing the obtained item of said user information to said process. The user information controlling unit obtains the user information requested by the process of an application program and provides the user information to the process. Accordingly, the user information can be shared by the application programs and centrally controlled.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked body, first and second semiconductor pillars, a connecting portion, a first memory film, and a dividing portion. The stacked bodies include a plurality of electrode films stacked along a first axis and as interelectrode insulating film provided between the electrode films. The first and second semiconductor pillars penetrate through the first and second stacked bodies along the first axis, respectively. The connecting portion electrically connects the first and second semiconductor pillars. The first memory film is provided between the electrode film and the semiconductor pillar. The dividing portion electrically divides the first and second electrode films from each other between the first semiconductor pillar and the second semiconductor pillar, is in contact with the connecting portion, and includes a stacked film including a material used for the first memory film.

Abstract: A reflecting telescope includes a reflecting mirror having an image forming function, a correction optical system configured to receive light reflected at the reflecting mirror, and including a compound lens including a positive lens and a negative lens in which a difference of refractive indexes of materials is 0.5% or more, and configured to be moved in a direction having a component of a vertical direction with respect to an optical axis, an image sensor configured to receive the light through the correction optical system, a detecting unit configured to detect a driving amount of the compound lens, and a control unit configured to tilt the image sensor with respect to the optical axis based on the driving amount of the compound lens detected by the detecting unit.

Abstract: A wire harness includes a wire bundle, an elongated object, and a covering member. The covering member is made of a single sheet-shaped nonwoven member and covers the wire bundle and the elongated object. The covering member includes a first portion that is wound around the wire bundle and is hot-pressed, and a second portion that is continuous with the first portion and that covers the elongated object on the first portion.

Abstract: According to one embodiment, a non-volatile memory device includes abase layer, a first stacked unit and a second stacked unit disposed above the base layer and arranged in parallel to each other and spaced apart from each other in a first direction, in a plane parallel to the base layer, a first semiconductor layer penetrating the first stacked unit, a second semiconductor layer penetrating in the second stacked unit, the first memory film disposed between the first semiconductor layer and the first stacked unit, and a connecting portion disposed between the base layer and the first stacked unit and between the base layer and the second stacked unit and electrically connecting the first semiconductor layer and the second semiconductor layer. An end portion of the first semiconductor layer is positioned between the connecting portion and the base layer.

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor memory device. The method includes forming a first stopper film forming a lower gate layer, making a recess in the lower gate layer, filling a sacrificial film into the recess, forming a second stopper film, making an opening in the second stopper film, forming a stacked body. The stacked body includes electrode films and insulating films. The method includes, making a slit in the stacked body, making a hole in the stacked body, removing the sacrificial film via the hole, forming a memory film including a charge storage film. The method includes forming a channel body on a side wall of the memory film. An etching rate of the first stopper film and the second stopper film is lower than an etching rate of the electrode films and the insulating films.

Abstract: A wire harness has a wire bundle and a covering member formed of a hot-pressed nonwoven member and covering the wire bundle. The covering member has a plurality of first portions extending in an extending direction of the wire bundle and at least one second portion extending in the extending direction of the wire bundle and being softer than the plurality of first portions. The first portions and the second portion of the covering member are provided alternately in a circumferential direction of the wire bundle. The covering member is bent at the at least one second portion in the circumferential direction of the wire bundle.

Abstract: A wire harness includes a wire bundle and a sheathing member covering the wire bundle and configured from a nonwoven member that has been hot-pressed. The sheathing member includes a plurality of path regulators along each of an extension direction and a circumference direction of the wire bundle, the path regulators being capable of regulating a path of a long member to be arranged along a surface of the sheathing member.

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method includes forming a second stacked body on the planarized interlayer insulating film and on the uppermost stair. The second stacked body includes a second conductive film thicker than the first conductive film and a second insulating film stacked on the second conductive film. The method includes dividing the second stacked body into a select gate on the uppermost stair and a plurality of wall portions in a staircase region below the uppermost stair. The method includes forming a plurality of vias piercing the interlayer insulating film under a region between the wall portions and reaching the first conductive film of each of the stairs.