Abstract: According to one embodiment, a manufacturing method of a nonvolatile semiconductor storage device, includes: forming a plurality of structures above a semiconductor substrate, each of the plurality of structures being such that in a stacked film where a plurality of first semiconductor films and a plurality of second semiconductor films are stacked alternately at least the second semiconductor films are held by a semiconductor or conductor pillar member via a gate dielectric film; selectively removing the first semiconductor films from the stacked film while maintaining a state where the second semiconductor films are held by the pillar member for each of the structures; oxidizing an exposed surface for each of the structures after removing the first semiconductor films; and embedding an inter-layer dielectric film between the plurality of structures in which the exposed surface is oxidized.

Abstract: A semiconductor device according to an embodiment, includes a plurality of gate structures; a first dielectric film; and a second dielectric film. The first dielectric film crosslinks adjacent gate structures of the plurality of gate structures so as to form a cavity each above and below in a position between the adjacent gate structures. The second dielectric film is formed as if to cover the cavity above the first dielectric film between the adjacent gate structures.

Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp (21541/T).

Abstract: A semiconductor device subjected to an optical annealing process by radiation light whose principal wavelength is 1.5 ?m or less includes a circuit pattern region formed on a semiconductor substrate, and a dummy pattern region formed separately from the circuit pattern region on the semiconductor substrate. The circuit pattern region has an integrated circuit pattern containing a gate pattern related to a circuit operation. The dummy pattern region has dummy gate patterns that have the same structure as that of a gate pattern used in the integrated circuit pattern and the dummy gate patterns are repeatedly arranged with a pitch 0.4 times or less the principal wavelength.

Abstract: According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer, two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer, select gate lines extending in the first direction on the first semiconductor layer, and word lines extending in the second direction on the select gate lines. The select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction. Each of the word lines is commonly connected to the control gates arranged in the second direction.

Abstract: According to one embodiment, a manufacturing method of a nonvolatile semiconductor storage device, includes: forming a plurality of structures above a semiconductor substrate, each of the plurality of structures being such that in a stacked film where a plurality of first semiconductor films and a plurality of second semiconductor films are stacked alternately at least the second semiconductor films are held by a semiconductor or conductor pillar member via a gate dielectric film; selectively removing the first semiconductor films from the stacked film while maintaining a state where the second semiconductor films are held by the pillar member for each of the structures; oxidizing an exposed surface for each of the structures after removing the first semiconductor films; and embedding an inter-layer dielectric film between the plurality of structures in which the exposed surface is oxidized.

Abstract: A semiconductor device has a semiconductor layer, a plurality of charge-accumulating layers formed at a predetermined interval from each other on said semiconductor layer through a first insulating film, a second insulating film formed on said charge-accumulating layer, a control gate including a silicide film formed on said second insulating film, a third insulating film formed between said control gates so that the top surface of said third insulating film is lower than the top surface of said control gate but is higher than the top surface of said second insulating film, a fourth insulating film formed into a concave shape so as to cover the top surface of said third insulating film and the side surfaces of said control gate positioned higher than the top surface of said third insulating film, and a fifth insulating film formed on said control gate and said fourth insulating film.

Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp (21541/T).

Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp(21541/T).

Abstract: A semiconductor device having a silicide film above source-drain regions comprises an element isolation insulating film which is provided so as to enclose an element forming region of a semiconductor substrate whose main component is silicon and contains silicon oxide as a main component, a gate electrode which is formed above the element forming region via a gate insulating film, diffused layers which are formed in the semiconductor substrate so as to sandwich a channel region below the gate electrode, semiconductor regions which are formed so as to sandwich the channel region and diffused regions and are composed of semiconductor material whose lattice constant differs from that of silicon, a silicon nitride film which is formed between the semiconductor regions and the element isolation insulating film and above the lowest part of the semiconductor regions, and a conducting film which is formed at the surface of the semiconductor regions.

Abstract: A semiconductor integrated circuit includes a rectangular low speed circuit area including a low speed circuit comprising a low speed transistor having a first source extension region and a first drain extension region, and a rectangular high speed circuit area adjacent to the low speed circuit area and including a high speed circuit comprising a high speed transistor having a second source extension region and a second drain extension region thinner than the first source and drain extension regions.

Abstract: The present invention discloses a semiconductor device and a manufacturing method thereof which improves its characteristics even though it is miniaturized. According to one aspect of the present invention, it is provided a semiconductor device comprising a first semiconductor element device including a pair of first diffusion layers formed in the semiconductor substrate with a first gate electrode therebetween, and a first conductor layer formed in the first diffusion layer and having an internal stress in a first direction, and a second semiconductor element device including a pair of second diffusion layers formed in the semiconductor substrate with a second gate electrode therebetween, and a second conductor layer formed in the second diffusion layer, having an internal stress in a second direction opposite to the first direction, and constituted of the same element as that of the first conductor layer.

Abstract: Disclosed is a method for manufacturing a semiconductor device comprising implanting ions of an impurity element into a semiconductor region, implanting, into the semiconductor region, ions of a predetermined element which is a group IV element or an element having the same conductivity type as the impurity element and larger in mass number than the impurity element, and irradiating a region into which the impurity element and the predetermined element are implanted with light to anneal the region, the light having an emission intensity distribution, a maximum point of the distribution existing in a wavelength region of not more than 600 nm.

Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp(21541/T).

Abstract: The present invention discloses a semiconductor device and a manufacturing method thereof which improves its characteristics even though it is miniaturized. According to one aspect of the present invention, it is provided a semiconductor device comprising a first semiconductor element device including a pair of first diffusion layers formed in the semiconductor substrate with a first gate electrode therebetween, and a first conductor layer formed in the first diffusion layer and having an internal stress in a first direction, and a second semiconductor element device including a pair of second diffusion layers formed in the semiconductor substrate with a second gate electrode therebetween, and a second conductor layer formed in the second diffusion layer, having an internal stress in a second direction opposite to the first direction, and constituted of the same element as that of the first conductor layer.

Abstract: A semiconductor device manufacturing method is disclosed. A silicon-containing gate electrode is first formed above the surface of a silicon-containing semiconductor substrate. Then, a sidewall insulating film is formed on the sidewall of the gate electrode and a film of metal is formed on the semiconductor substrate to cover the gate electrode and the sidewall insulating film. The front and back sides of the semiconductor substrate are heated through heat conduction by an ambient gas. Thereby, the metal is caused to react with silicon contained in the semiconductor substrate and the gate electrode to form a metal silicide film.

Abstract: A semiconductor device subjected to an optical annealing process by radiation light whose principal wavelength is 1.5 ?m or less includes a circuit pattern region formed on a semiconductor substrate, and a dummy pattern region formed separately from the circuit pattern region on the semiconductor substrate. The circuit pattern region has an integrated circuit pattern containing a gate pattern related to a circuit operation. The dummy pattern region has dummy gate patterns that have the same structure as that of a gate pattern used in the integrated circuit pattern and the dummy gate patterns are repeatedly arranged with a pitch 0.4 times or less the principal wavelength.

Abstract: A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells each having a double-layered gate structure in which a floating gate and a control gate formed of a nickel silicide film are laminated, a first contact plug formed on a substrate contact portion of a surface of the semiconductor substrate, the first contact plug having a lower layer formed of a semiconductor film and an upper layer formed of a nickel silicide film, and second contact plugs formed on the control gates and first contact plug.

Abstract: A semiconductor device includes a silicon region including Si, and a silicide film provided on the silicon region, the silicide film comprising a compound of Si with Ni, Co, Pd, or Pt and including Er.

Abstract: A semiconductor device has a semiconductor layer, a plurality of charge-accumulating layers formed at a predetermined interval from each other on said semiconductor layer through a first insulating film, a second insulating film formed on said charge-accumulating layer, a control gate including a silicide film formed on said second insulating film, a third insulating film formed between said control gates so that the top surface of said third insulating film is lower than the top surface of said control gate but is higher than the top surface of said second insulating film, a fourth insulating film formed into a concave shape so as to cover the top surface of said third insulating film and the side surfaces of said control gate positioned higher than the top surface of said third insulating film, and a fifth insulating film formed on said control gate and said fourth insulating film.