Abstract: In a semiconductor device in which the gate electrode of a MISFET formed on a semiconductor substrate is electrically connected to a well region under the channel of the MISFET, the MISFET is formed in an island-shaped element region formed on the semiconductor substrate, and electrical connection between the gate electrode of the MISFET and the well region in the semiconductor substrate is done on the side surface of the island-shaped element region.

Abstract: A semiconductor device includes an element separating insulating film provided on a semiconductor substrate to separate an element region. A gate electrode is arranged above the element region. Source/drain regions are formed in the semiconductor substrate to sandwich a region below the gate electrode. A silicide film is provided on the source/drain regions, extending onto the element separating insulating film. A contact hole extends through the interlayer insulating film, which is provided on the element separating insulating film and the silicide film, and reaches the silicide film. Ends of the contact hole are positioned on the silicide film and on the element separating insulating film. The contact hole includes a trench portion whose one end contacts with the edge of the silicide film in the bottom of the contact hole and in an upper portion of the element separating insulating film. A wiring layer is arranged in the contact hole.

Abstract: A semiconductor device has a MOSFET. The MOSFET includes source and drain regions, a gate insulating film, a gate electrode, and first, second, and third metal silicide films. The source and drain regions are formed in the major surface region of a semiconductor substrate. The gate insulating film is formed on the channel region between the source and drain regions. The gate electrode is formed on the gate insulating film and includes a poly-Si1−xGex layer having a Ge/(Si+Ge) composition ratio x (0<x<0.2). The first metal silicide film is formed on the gate electrode and made of NiSi1−yGey. The second and third metal silicide films are formed on the source and drain regions, respectively, and made of NiSi.

Abstract: A semiconductor device includes an element separating insulating film provided on a semiconductor substrate to separate an element region. A gate electrode is arranged above the element region. Source/drain regions are formed in the semiconductor substrate to sandwich a region below the gate electrode. A silicide film is provided on the source/drain regions, extending onto the element separating insulating film. A contact hole extends through the interlayer insulating film, which is provided on the element separating insulating film and the silicide film, and reaches the silicide film. Ends of the contact hole are positioned on the silicide film and on the element separating insulating film. The contact hole includes a trench portion whose one end contacts with the edge of the silicide film in the bottom of the contact hole and in an upper portion of the element separating insulating film. A wiring layer is arranged in the contact hole.

Abstract: A semiconductor device includes a semiconductor substrate, a gate insulator film formed on a bottom surface and a side surface of a groove formed in the semiconductor substrate, a gate electrode having a lower portion buried in the groove on whose bottom and side surface the gate insulator film is formed, and an upper portion protruding a surface of said semiconductor substrate, and source region and a drain region formed on a surface of the semiconductor substrate in such a way as to sandwich the gate electrode. A thickness of the upper portion of the gate electrode protruding the surface of the semiconductor substrate is equal to or greater than twice a thickness of the lower portion of the gate electrode buried in the groove.

Abstract: Disclosed is a method for manufacturing a semiconductor device comprising implanting ions of an impurity element into a semiconductor region, implanting, into the semiconductor region, ions of a predetermined element which is a group IV element or an element having the same conductivity type as the impurity element and larger in mass number than the impurity element, and irradiating a region into which the impurity element and the predetermined element are implanted with light to anneal the region, the light having an emission intensity distribution, a maximum point of the distribution existing in a wavelength region of not more than 600 nm.

Abstract: To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first film and a second film on a semiconductor substrate, selectively removing the second film, the first film and a top portion of the semiconductor substrate to form a first groove, burying a first insulator film in the first groove to form an isolation region, patterning the second film surrounded by the isolation region to form a dummy gate layer, doping the semiconductor substrate with an impurity using the dummy gate layer as a mask, forming a second insulator film on the semiconductor substrate surrounded by the dummy gate layer and the first insulator film, removing the dummy gate layer and the first film to form a second groove, forming a gate insulator film on the semiconductor substrate in the second groove, and forming a gate electrode on the gate insulator film in the second groove.

Abstract: To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.

Abstract: A method of manufacturing semiconductor device comprises the steps of forming a first film and a second film on a semiconductor substrate, selectively removing the second film, the first film and a top portion of the semiconductor substrate to form a first groove, burying a first insulator film in the first groove to form an isolation region, patterning the second film surrounded by the isolation region to form a dummy gate layer, doping the semiconductor substrate with an impurity using the dummy gate layer as a mask, forming a second insulator film on the semiconductor substrate surrounded by the dummy gate layer and the first insulator film, removing the dummy gate layer and the first film to form a second groove, forming a gate insulator film on the semiconductor substrate in the second groove, and forming a gate electrode on the gate insulator film in the second groove.

Abstract: In a semiconductor device in which the gate electrode of a MISFET formed on a semiconductor substrate is electrically connected to a well region under the channel of the MISFET, the MISFET is formed in an island-shaped element region formed on the semiconductor substrate, and electrical connection between the gate electrode of the MISFET and the well region in the semiconductor substrate is done on the side surface of the island-shaped element region.

Abstract: In a semiconductor device in which the gate electrode of a MISFET formed on a semiconductor substrate is electrically connected to a well region under the channel of the MISFET, the MISFET is formed in an island-shaped element region formed on the semiconductor substrate, and electrical connection between the gate electrode of the MISFET and the well region in the semiconductor substrate is done on the side surface of the island-shaped element region.

Abstract: Disclosed is a semiconductor device having an N-type MIS transistor formed in a first region and a P-type MIS transistor formed in a second region, wherein, the N-type MIS transistor includes a first gate insulating film formed on at least the bottom of a first concave portion formed in the first region and a first gate electrode formed on the first gate insulating film, the P-type MIS transistor includes a second gate insulating film formed on at least the bottom of a second concave portion formed in the second region and a second gate electrode formed on the second gate insulating film, each of the first and second gate electrodes includes at least one metal-containing film, and at least one of the first and second gate electrodes is of a laminate structure including a plurality of the metal-containing films, and the work function of the metal-containing film constituting at least a part of the first gate electrode and in contact with the first gate insulating film is smaller than the work function of the m

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first film and a second film on a semiconductor substrate, selectively removing the second film, the first film and a top portion of the semiconductor substrate to form a first groove, burying a first insulator film in the first groove to form an isolation region, patterning the second film surrounded by the isolation region to form a dummy gate layer, doping the semiconductor substrate with an impurity using the dummy gate layer as a mask, forming a second insulator film on the semiconductor substrate surrounded by the dummy gate layer and the first insulator film, removing the dummy gate layer and the first film to form a second groove, forming a gate insulator film on the semiconductor substrate in the second groove, and forming a gate electrode on the gate insulator film in the second groove.

Abstract: A silicon region partitioned by insulating films is formed on a main surface of a substrate. A mixed film of first and second metals is formed directly or indirectly on the substrate having the silicon region formed thereon. Then, a heat treatment is applied to permit the first and second metals to react with silicon in the silicon region so as to form selectively a first silicide film on the surface of the silicon region. Further, the first silicide film is subjected to a heat treatment under a nitriding atmosphere so as to form a second silicide film consisting essentially of the first metal and silicon on the surface of the silicon region and a nitride film consisting essentially of the second metal and nitrogen on the surface of the second silicide film or both on the surface and at the crystal grain boundary of the second silicide film.

Abstract: A bipolar transistor is formed on a silicon substrate having a silicon oxide film. An n-silicon layer having a top surface of a (100) plane is formed on the silicon oxide film and is used as a collector layer. An end face constituted by a (111) plane is formed on the end portion of the collector layer by etching, using an aqueous KOH solution. A B-doped p-silicon layer is formed on the end face by epitaxial growth and is used as a base layer. Furthermore, an As-doped n-silicon layer is formed on the base layer and is used as an emitter layer. Electrodes are respectively connected to the collector, base, and emitter layers.

Abstract: A bipolar transistor is formed on a silicon substrate having a silicon oxide film. An n-silicon layer having a top surface of a (100) plane is formed on the silicon oxide film and is used as a collector layer. An end face constituted by a (111) plane is formed on the end portion of the collector layer by etching, using an aqueous KOH solution. A B-doped p-silicon layer is formed on the end face by epitaxial growth and is used as a base layer. Furthermore, an As-doped n-silicon layer is formed on the base layer and is used as an emitter layer. Electrodes are respectively connected to the collector, base, and emitter layers.