Patents by Inventor Toshio Nakajima
Toshio Nakajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180012987Abstract: A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.Type: ApplicationFiled: August 14, 2017Publication date: January 11, 2018Applicant: ROHM CO., LTD.Inventor: Toshio NAKAJIMA
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Patent number: 9755065Abstract: A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.Type: GrantFiled: June 4, 2016Date of Patent: September 5, 2017Assignee: ROHM CO., LTD.Inventor: Toshio Nakajima
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Patent number: 9536948Abstract: A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.Type: GrantFiled: March 31, 2016Date of Patent: January 3, 2017Assignee: ROHM CO., LTD.Inventor: Toshio Nakajima
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Patent number: 9490359Abstract: A semiconductor device that includes the following is manufactured: an n? base layer; a p-type base layer formed on the surface of the n? base layer; an n+ source layer formed in the inner area of the p-type base layer; a gate electrode formed so as to face a channel region across a gate insulating film; a plurality of p-type columnar regions that are formed in the n? base layer so as to continue from the p-type base layer and that are arranged at a first pitch; and a plurality of p+ collector layers that are selectively formed on the rear surface of the n? base layer and that are arranged at a second pitch larger than the first pitch.Type: GrantFiled: April 24, 2015Date of Patent: November 8, 2016Assignee: ROHM CO., LTD.Inventor: Toshio Nakajima
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Publication number: 20160284835Abstract: A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.Type: ApplicationFiled: June 4, 2016Publication date: September 29, 2016Applicant: ROHM CO., LTD.Inventor: Toshio NAKAJIMA
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Publication number: 20160211323Abstract: A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.Type: ApplicationFiled: March 31, 2016Publication date: July 21, 2016Applicant: ROHM CO., LTD.Inventor: Toshio NAKAJIMA
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Patent number: 9385217Abstract: A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.Type: GrantFiled: July 1, 2014Date of Patent: July 5, 2016Assignee: Rohm Co., Ltd.Inventor: Toshio Nakajima
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Patent number: 9324857Abstract: A semiconductor device includes a p-type semiconductor layer, n-type column regions formed of columnar thermal donors exhibiting an n-type property, a p-type column region interposed between the n-type column regions, the n-type column regions configured to form a super-junction structure in cooperation with the p-type column region, a channel region formed in the semiconductor layer, a source region formed in the channel region, a gate insulator film formed on the semiconductor layer, and a gate electrode formed on the gate insulator film and opposite to the channel region across the gate insulator film.Type: GrantFiled: April 10, 2015Date of Patent: April 26, 2016Assignee: ROHM CO., LTD.Inventor: Toshio Nakajima
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Patent number: 9306000Abstract: A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.Type: GrantFiled: October 6, 2015Date of Patent: April 5, 2016Assignee: ROHM CO., LTD.Inventor: Toshio Nakajima
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Publication number: 20160035824Abstract: A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.Type: ApplicationFiled: October 6, 2015Publication date: February 4, 2016Applicant: ROHM CO., LTD.Inventor: Toshio NAKAJIMA
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Publication number: 20150363351Abstract: A data transfer device performing data transfer at a high speed if a descriptor chain cannot be entirely transferred by a single activation. In a DMA control device, when a transfer activation signal is asserted, a descriptor information control part sequentially reads descriptor information from a descriptor information storage part. When the count of pieces of descriptor information that have been read becomes equal to a transferable frame count, a backward skip control part outputs a backward skip instruction. When the backward skip instruction is outputted, a descriptor information control part skips reading remaining descriptor information.Type: ApplicationFiled: April 10, 2013Publication date: December 17, 2015Applicant: Mitsubishi Electric CorporationInventors: Hidenori SATO, Toshio NAKAJIMA
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Patent number: 9184231Abstract: A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.Type: GrantFiled: June 15, 2015Date of Patent: November 10, 2015Assignee: ROHM CO., LTD.Inventor: Toshio Nakajima
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Publication number: 20150290865Abstract: A blow molding machine includes a support member and a moving mechanism that moves the support member to a projecting position a storing position. The blow molding machine includes a first fixed fulcrum shaft, and the support member includes a base end portion rotatably supported by the first fixed fulcrum shaft and a free end portion provided with a first movable fulcrum shaft. The moving mechanism includes a plurality of links connected rotatably to each other, one of the plurality of links being rotatably supported by the movable fulcrum shaft of the support member, and, when the support member is set at the projecting position, the plurality of links are maintained linearly by a first angle fixing tool, thereby enabling the plurality of links to serve as a leg portion that supports the free end portion of the support member.Type: ApplicationFiled: October 22, 2012Publication date: October 15, 2015Inventors: Hiroshi Horigome, Toshio Nakajima
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Publication number: 20150279932Abstract: A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.Type: ApplicationFiled: June 15, 2015Publication date: October 1, 2015Applicant: ROHM CO., LTD.Inventor: Toshio NAKAJIMA
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Publication number: 20150228784Abstract: A semiconductor device that includes the following is manufactured: an n? base layer; a p-type base layer formed on the surface of the n? base layer; an n+ source layer formed in the inner area of the p-type base layer; a gate electrode formed so as to face a channel region across a gate insulating film; a plurality of p-type columnar regions that are formed in the n? base layer so as to continue from the p-type base layer and that are arranged at a first pitch; and a plurality of p+ collector layers that are selectively formed on the rear surface of the n? base layer and that are arranged at a second pitch larger than the first pitch.Type: ApplicationFiled: April 24, 2015Publication date: August 13, 2015Applicant: ROHM CO., LTD.Inventor: Toshio NAKAJIMA
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Publication number: 20150221763Abstract: A semiconductor device includes a p-type semiconductor layer, n-type column regions formed of columnar thermal donors exhibiting an n-type property, a p-type column region interposed between the n-type column regions, the n-type column regions configured to form a super-junction structure in cooperation with the p-type column region, a channel region formed in the semiconductor layer, a source region formed in the channel region, a gate insulator film formed on the semiconductor layer, and a gate electrode formed on the gate insulator film and opposite to the channel region across the gate insulator film.Type: ApplicationFiled: April 10, 2015Publication date: August 6, 2015Applicant: ROHM CO., LTD.Inventor: Toshio NAKAJIMA
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Patent number: 9087857Abstract: A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.Type: GrantFiled: December 15, 2014Date of Patent: July 21, 2015Assignee: ROHM CO., LTD.Inventor: Toshio Nakajima
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Patent number: 9041096Abstract: A semiconductor device that includes the following is manufactured: an n? base layer; a p-type base layer formed on the surface of the n? base layer; an n+ source layer formed in the inner area of the p-type base layer; a gate electrode formed so as to face a channel region across a gate insulating film; a plurality of p-type columnar regions that are formed in the n? base layer so as to continue from the p-type base layer and that are arranged at a first pitch; and a plurality of p+ collector layers that are selectively formed on the rear surface of the n? base layer and that are arranged at a second pitch larger than the first pitch.Type: GrantFiled: April 8, 2014Date of Patent: May 26, 2015Assignee: ROHM CO., LTD.Inventor: Toshio Nakajima
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Publication number: 20150140754Abstract: A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.Type: ApplicationFiled: December 15, 2014Publication date: May 21, 2015Inventor: Toshio NAKAJIMA
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Patent number: 9029207Abstract: A semiconductor device includes a p-type semiconductor layer, n-type column regions formed of columnar thermal donors exhibiting an n-type property, a p-type column region interposed between the n-type column regions, the n-type column regions configured to form a super-junction structure in cooperation with the p-type column region, a channel region formed in the semiconductor layer, a source region formed in the channel region, a gate insulator film formed on the semiconductor layer, and a gate electrode formed on the gate insulator film and opposite to the channel region across the gate insulator film.Type: GrantFiled: July 3, 2014Date of Patent: May 12, 2015Assignee: Rohm Co., Ltd.Inventor: Toshio Nakajima