Patents by Inventor Toshio Negishi

Toshio Negishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10189249
    Abstract: A recording element substrate includes a recording module including a plurality of recording elements and first logic circuits corresponding to the plurality of recording elements, a memory module including a plurality of memory elements and second logic circuits corresponding to the plurality of memory elements, and a common line configured to connect a signal supply circuit to the plurality of first logic circuits and the plurality of second logic circuits in common. The recording elements are arranged along an extending direction in which the common line extends, and the memory modules are disposed between the common line and the recording elements.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: January 29, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Suguru Taniguchi, Toshio Negishi, Kazunari Fujii
  • Patent number: 10147720
    Abstract: A semiconductor device includes a transistor connected to a terminal having a first potential, an anti-fuse element connected between the transistor and a terminal having a second potential different from the first potential, and a resistor element connected in parallel with the anti-fuse element. An electric path between the transistor and the anti-fuse element has a length smaller than a length of an electric path between the transistor and the resistor element.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: December 4, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazunari Fujii, Toshio Negishi
  • Publication number: 20180281390
    Abstract: An apparatus includes a substrate, a transistor provided on the substrate and connected to a first terminal supplied with a first voltage, an anti-fuse element provided on the substrate and connected between the transistor and a second terminal supplied with a second voltage, a first resistive element provided on the substrate and connected in parallel to the anti-fuse element and between the transistor and the second terminal, and an adjusting unit provided on the substrate and configured to function so as to reduce an influence of variation in resistance of the first resistive element in reading out of information from the anti-fuse element.
    Type: Application
    Filed: March 21, 2018
    Publication date: October 4, 2018
    Inventors: Kazunari Fujii, Naoki Isoda, Toshio Negishi, Wataru Endo
  • Publication number: 20180236761
    Abstract: A recording element substrate includes a recording module including a plurality of recording elements and first logic circuits corresponding to the plurality of recording elements, a memory module including a plurality of memory elements and second logic circuits corresponding to the plurality of memory elements, and a common line configured to connect a signal supply circuit to the plurality of first logic circuits and the plurality of second logic circuits in common. The recording elements are arranged along an extending direction in which the common line extends, and the memory modules are disposed between the common line and the recording elements.
    Type: Application
    Filed: February 13, 2018
    Publication date: August 23, 2018
    Inventors: Suguru Taniguchi, Toshio Negishi, Kazunari Fujii
  • Publication number: 20180236762
    Abstract: A recording element substrate includes a signal supply circuit and a common line which connects the signal supply circuit to first logic circuit array for a recording element and a second logic circuit array for a memory element in common. Furthermore, the first and second logic circuit arrays extend along a direction in which the common line extends, the first logic circuit array is disposed on one side of the common line, the second logic circuit array is disposed on the other side of the common line, and the first and second logic circuit arrays are arranged so that at least a portion of the first logic circuit array and a portion of the second logic circuit array overlap with each other in a direction orthogonal to the extending direction.
    Type: Application
    Filed: February 21, 2018
    Publication date: August 23, 2018
    Inventors: Toshio Negishi, Suguru Taniguchi, Kazunari Fujii
  • Patent number: 9950525
    Abstract: An element substrate for a liquid ejecting head includes a substrate, an element forming layer on the substrate, and a discharge port forming member formed of an insulating member on the element forming layer. The element forming layer includes an energy generating element configured to provide energy to a liquid for ejection. The discharge port forming member includes a discharge port forming surface having discharge ports through which the liquid is ejected and an exterior side surface positioned between the discharge port forming surface and the element forming layer. The exterior side surface has a first edge facing the element forming layer. The element substrate further includes a conductive layer disposed between the first edge and the element forming layer and grounded.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: April 24, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Ryoji Oohashi, Koichi Omata, Hideo Tamura, Takaaki Yamaguchi, Kousuke Kubo, Suguru Taniguchi, Yuji Tamaru, Toshio Negishi, Yohei Osuki
  • Publication number: 20180104954
    Abstract: A print element substrate, comprises: a heater layer; a wiring layer that is connected to the heater layer and is for causing the heater layer to generate heat; an insulating layer arranged on the wiring layer; an anti-cavitation layer arranged on the insulating layer that is for protecting the insulating layer; and a switch that has a control terminal that is pulled-down to a ground, and causes the anti-cavitation layer and the ground to have an electrical connection when the control terminal is in a high-level state.
    Type: Application
    Filed: August 31, 2017
    Publication date: April 19, 2018
    Inventors: Yohei Osuki, Koichi Omata, Hideo Tamura, Takaaki Yamaguchi, Kousuke Kubo, Ryoji Oohashi, Yuji Tamaru, Toshio Negishi, Suguru Taniguchi
  • Publication number: 20180061826
    Abstract: A semiconductor device includes a transistor connected to a terminal having a first potential, an anti-fuse element connected between the transistor and a terminal having a second potential different from the first potential, and a resistor element connected in parallel with the anti-fuse element. An electric path between the transistor and the anti-fuse element has a length smaller than a length of an electric path between the transistor and the resistor element.
    Type: Application
    Filed: August 29, 2017
    Publication date: March 1, 2018
    Inventors: Kazunari Fujii, Toshio Negishi
  • Publication number: 20180061506
    Abstract: A semiconductor apparatus includes a transistor connected to a first potential terminal having a first potential, an anti-fuse element connected between the transistor and a second potential terminal having a second potential, a resistive element connected in parallel with the anti-fuse element between the transistor and the second potential terminal, and a temperature adjustment unit disposed to face the resistive element.
    Type: Application
    Filed: August 16, 2017
    Publication date: March 1, 2018
    Inventors: Kazunari Fujii, Toshio Negishi
  • Patent number: 9895879
    Abstract: A semiconductor device includes, an anti-fuse element, a transistor connected via the anti-fuse element to a power source terminal which may apply a voltage to the anti-fuse element, an ESD protection element connected to the power source terminal via a node, and a first resistive element disposed in an electric path between the node and the anti-fuse element, wherein resistance of the first resistive element increases with an increase of a voltage applied to the first resistive element.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: February 20, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazunari Fujii, Toshio Negishi
  • Patent number: 9833992
    Abstract: A recording-element substrate includes a substrate including a base member, a pair of electrodes, a heating element formed of a thermal resistor layer between the electrodes, a surface on which an electroconductive film coating the heating element has been formed, and an insulating film between the heating element and the electroconductive film and a flow-path-forming member including walls forming a liquid flow path toward the heating element while being disposed on the substrate's surface side. The substrate includes an electric connecting portion in contact with the electroconductive film to connect the electroconductive film with the base member. The shortest distance between the electric connecting portion and a portion where an angle formed by the walls is 120 degrees or smaller when viewed from a direction orthogonal to the surface is smaller than that between a boundary between the electrodes and the heating element and the portion.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: December 5, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Suguru Taniguchi, Koichi Omata, Hideo Tamura, Takaaki Yamaguchi, Kousuke Kubo, Ryoji Oohashi, Yuji Tamaru, Toshio Negishi, Yohei Osuki
  • Publication number: 20170173953
    Abstract: A recording-element substrate includes a substrate including a base member, a pair of electrodes, a heating element formed of a thermal resistor layer between the electrodes, a surface on which an electroconductive film coating the heating element has been formed, and an insulating film between the heating element and the electroconductive film and a flow-path-forming member including walls forming a liquid flow path toward the heating element while being disposed on the substrate's surface side. The substrate includes an electric connecting portion in contact with the electroconductive film to connect the electroconductive film with the base member. The shortest distance between the electric connecting portion and a portion where an angle formed by the walls is 120 degrees or smaller when viewed from a direction orthogonal to the surface is smaller than that between a boundary between the electrodes and the heating element and the portion.
    Type: Application
    Filed: December 16, 2016
    Publication date: June 22, 2017
    Inventors: Suguru Taniguchi, Koichi Omata, Hideo Tamura, Takaaki Yamaguchi, Kousuke Kubo, Ryoji Oohashi, Yuji Tamaru, Toshio Negishi, Yohei Osuki
  • Publication number: 20170173943
    Abstract: A semiconductor device includes, an anti-fuse element, a transistor connected via the anti-fuse element to a power source terminal which may apply a voltage to the anti-fuse element, an ESD protection element connected to the power source terminal via a node, and a first resistive element disposed in an electric path between the node and the anti-fuse element, wherein resistance of the first resistive element increases with an increase of a voltage applied to the first resistive element.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 22, 2017
    Inventors: Kazunari Fujii, Toshio Negishi
  • Publication number: 20170100930
    Abstract: An element substrate for a liquid ejecting head includes a substrate, an element forming layer on the substrate, and a discharge port forming member formed of an insulating member on the element forming layer. The element forming layer includes an energy generating element configured to provide energy to a liquid for ejection. The discharge port forming member includes a discharge port forming surface having discharge ports through which the liquid is ejected and an exterior side surface positioned between the discharge port forming surface and the element forming layer. The exterior side surface has a first edge facing the element forming layer. The element substrate further includes a conductive layer disposed between the first edge and the element forming layer and grounded.
    Type: Application
    Filed: October 6, 2016
    Publication date: April 13, 2017
    Inventors: Ryoji Oohashi, Koichi Omata, Hideo Tamura, Takaaki Yamaguchi, Kousuke Kubo, Suguru Taniguchi, Yuji Tamaru, Toshio Negishi, Yohei Osuki
  • Patent number: 9522529
    Abstract: A substrate includes an AND circuit and an LVC. The AND circuit generates a control signal for switching an NMOS transistor. The LVC controls the gate voltage of the NMOS transistor on the basis of the control signal. The substrate applies a constant gate voltage to a PMOS transistor without using the AND circuit and the LVC.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: December 20, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takaaki Yamaguchi, Toshio Negishi, Taku Yokozawa, Hiroaki Shirakawa, Kazunari Fujii
  • Publication number: 20160288494
    Abstract: A substrate includes an AND circuit and an LVC. The AND circuit generates a control signal for switching an NMOS transistor. The LVC controls the gate voltage of the NMOS transistor on the basis of the control signal. The substrate applies a constant gate voltage to a PMOS transistor without using the AND circuit and the LVC.
    Type: Application
    Filed: March 24, 2016
    Publication date: October 6, 2016
    Inventors: Takaaki Yamaguchi, Toshio Negishi, Taku Yokozawa, Hiroaki Shirakawa, Kazunari Fujii
  • Patent number: 8876242
    Abstract: A print head is provided that well preserves ink characteristics upon printing by way of performing effective ink preliminary heating. The print head has heaters and ejection openings formed at locations corresponding to the heaters. Viewed from the side from which ink is ejected, a sub-heater is established in the print head between the ink supply port and the print elements so as to surround the ink supply port.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: November 4, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yuuji Tamaru, Yoshiyuki Imanaka, Koichi Omata, Hideo Tamura, Takaaki Yamaguchi, Kousuke Kubo, Ryoji Oohashi, Toshio Negishi, Tatsuo Furukawa, Nobuyuki Hirayama, Ryo Kasai, Tomoko Kudo
  • Patent number: 8523324
    Abstract: A liquid discharge head substrate includes an external terminal, a diode, a first conductive layer, a second conductive layer, and a third conductive layer. The external terminal is configured to connect to an external. The first conductive layer is connected to the external terminal for causing an input current to flow from the external terminal, and the diode includes an anode and a cathode. The second conductive layer is connected to the first conductive layer and one electrode of the anode and cathode, and causes a surge current generated when a surge voltage is applied from the external terminal, to flow from the first conductive layer to the one electrode. The third conductive layer is connected to the other electrode of the anode and the cathode and passes the surge current flowing from the one electrode to the other electrode.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: September 3, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takaaki Yamaguchi, Yoshiyuki Imanaka, Koichi Omata, Toshio Negishi
  • Patent number: 8420169
    Abstract: A thin film of a uniform film thickness is formed even without increasing the film deposition rate. The temperature of an evaporation device disposed in an evaporation chamber is raised in advance, and an organic material is dropped from a supply unit onto an evaporation surface of the evaporation device; and when the organic material is evaporated, a heated carrier gas is introduced into the evaporation chamber, and is mixed in the evaporation chamber and is introduced into a discharger. While a molecular flow is formed in the discharger in a case that only the organic material vapor is introduced into the discharger, the pressure within the discharger is raised due to the carrier gas, so that a viscous flow is formed and the mixed gas is filled in the discharger and is uniformly discharged. The organic material may be supplied by a small amount and the film deposition rate may not become too high.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: April 16, 2013
    Assignee: Ulvac, Inc.
    Inventor: Toshio Negishi
  • Patent number: 8334647
    Abstract: A technology is provided, which obtains an organic EL device free from any reduction in the luminescent efficiency, even if an electrode layer is formed on a surface of a charge injection layer by a sputtering method. An organic EL device of the present invention includes a first charge injection layer, a first organic layer, and a second charge injection layer. The second charge injection layer is formed as a mixed layer in which a matrix organic material and a charge injectable metallic material are mixed. Even when the electrode layer is formed on a surface of this second charge injection layer by the sputtering method, the luminescent efficiency does not decrease.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: December 18, 2012
    Assignee: Ulvac, Inc.
    Inventor: Toshio Negishi