Abstract: An olefin polymer that is obtained using an olefin polymerization catalyst that includes a solid catalyst component for olefin polymerization that includes titanium, magnesium, a halogen, and an ester compound (A) represented by the following formula (1): R1R2C?C(COOR3)(COOR4), an organoaluminum compound, and an optional external electron donor compound, exhibits primary properties (e.g., molecular weight distribution and stereoregularity) similar to those of an olefin polymer obtained using a solid catalyst component that includes a phthalic ester as an electron donor.

Abstract: A method for producing a solid catalyst component for olefin polymerization includes bringing a magnesium compound, a tetravalent titanium halide compound, and an electron donor compound represented by a general formula (1) into contact with each other, reacting the mixture, washing the resulting reaction product to obtain a solid component, bringing the solid component, a tetravalent titanium halide compound, and an electron donor compound represented by a general formula (2) into contact with each other, reacting the mixture, and washing the resulting reaction product. (R1)kC6H4-k(COOR2)(COOR3)??(1) R4R5C(COOR6)2??(2) A polymer that exhibits high activity with respect to hydrogen, high stereoregularity, and high bulk density can be obtained using a catalyst including a solid catalyst component obtained by the method.

Abstract: In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.

Abstract: A solid catalyst component for olefin polymerization and a catalyst are disclosed that exhibit high catalytic activity when used for gas-phase polymerization, suppress rapid reactions in the initial stage of polymerization relative to the polymerization activity, and can produce a propylene polymer in high yield while maintaining high stereoregularity. The solid catalyst component for olefin polymerization includes magnesium, titanium, a halogen, and an internal electron donor, the solid catalyst component including an asymmetrical phthalic diester represented by the following general formula (1) in a molar ratio of 0.2 to 0.8 relative to the total content of the internal electron donor.

Abstract: A semiconductor device includes a controlled oscillator and a control unit. The controlled oscillator includes a resonance circuit, an amplification unit, and a current adjustment unit. The resonance circuit includes one or a plurality of inductors and a first capacitive unit having a variable capacitance value. The amplification unit is connected to the resonance circuit, and outputs a local oscillation signal having an oscillation frequency corresponding to a resonance frequency of the resonance circuit. The current adjustment unit adjusts a value of a drive current to be supplied to the amplification unit. The control unit controls the capacitance value of the first capacitive unit and the current adjustment unit. When the control unit instructs the current adjustment unit to change the value of the drive current to be supplied to the amplification unit, the control unit also changes the capacitance value of the first capacitive unit.

Abstract: A conventional semiconductor device has a problem that acquisition of variation information of circuit elements constructing the semiconductor device is not easy. According to an embodiment, a semiconductor device has a control circuit which makes an oscillation circuit operate by at least two operation current values, obtains first frequency information related to frequency of an output signal corresponding to a first operation current value and second frequency information related to frequency of an output signal corresponding to a second operation current value, and obtains manufacture variation information of a circuit element on the basis of the difference between the first and second frequency information.

Abstract: A high frequency signal processing device is capable of carrying out high-accuracy modulation by a PLL circuit. A digital loop is configured in addition to an analog loop having, for example, a phase frequency detector, a charge pump circuit, and a loop filter. A digital calibration circuit is provided which searches for the optimal code set to a capacitor bank upon frequency modulation. Upon the search for the optimal code, a calibration controller first sets a division ratio based on a center frequency to a divider and determines the value of a voltage control signal using the analog loop. Then, the loop filter holds the value of the voltage control signal therein, and a division ratio corresponding to a “center frequency+modulated portion” is set to the divider, thereby operating the digital loop. The optimal code is obtained by a convergent value of the digital loop.

Abstract: To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.

Abstract: A PLL circuit of which low power consumption and miniaturization are satisfied at the same time is provided. A phase comparator of the PLL circuit includes a counter and a time-to-digital converter. The counter receives a reference clock signal and a low frequency clock signal obtained by dividing an output of a digital controlled oscillator, and a high frequency clock signal. The counter detects a phase difference between the reference clock signal and the low frequency clock signal by counting the clock number of the high frequency clock signal. The time-to-digital converter receives the reference clock signal and the low frequency clock signal. The time-to-digital converter detects the phase difference between the reference clock signal and the low frequency clock signal to the accuracy of a time period shorter than a cycle of the high frequency clock signal, after the output of counter reaches a predetermined range.

Abstract: A high frequency signal processing device is capable of carrying out high-accuracy modulation by a PLL circuit. A digital loop is configured in addition to an analog loop having, for example, a phase frequency detector, a charge pump circuit, and a loop filter. A digital calibration circuit is provided which searches for the optimal code set to a capacitor bank upon frequency modulation. Upon the search for the optimal code, a calibration controller first sets a division ratio based on a center frequency to a divider and determines the value of a voltage control signal using the analog loop. Then, the loop filter holds the value of the voltage control signal therein, and a division ratio corresponding to a “center frequency+modulated portion” is set to the divider, thereby operating the digital loop. The optimal code is obtained by a convergent value of the digital loop.

Abstract: In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.

Abstract: A PLL circuit of which low power consumption and miniaturization are satisfied at the same time is provided. A phase comparator of the PLL circuit includes a counter and a time-to-digital converter. The counter receives a reference clock signal and a low frequency clock signal obtained by dividing an output of a digital controlled oscillator, and a high frequency clock signal. The counter detects a phase difference between the reference clock signal and the low frequency clock signal by counting the clock number of the high frequency clock signal. The time-to-digital converter receives the reference clock signal and the low frequency clock signal. The time-to-digital converter detects the phase difference between the reference clock signal and the low frequency clock signal to the accuracy of a time period shorter than a cycle of the high frequency clock signal, after the output of counter reaches a predetermined range.

Abstract: In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.

Abstract: A technique for suppressing quantization noise generated due to digitizing an analog circuit in a PLL circuit is provided. The PLL circuit comprises: a digital phase frequency detector which detects (compares) phases and frequencies of a reference signal and a frequency-divided signal and converts the same to a digital value; a digital loop filter which eliminates high-frequency noise components from an output of the digital phase frequency comparator; a digital-analog converter which converts a digital value of an output of the digital loop filter to an analog value; an analog filter which eliminates a high-frequency noise component from an output of the digital-analog converter; a voltage controlled oscillator whose frequency is controlled based on an output of the analog filter; and a frequency divider which divides the frequency of the voltage controlled oscillator and outputs the frequency-divided signal.

Abstract: The present invention provides a semiconductor integrated circuit capable of reducing a chip occupied area and reducing variations in control gain of a digitally controlled oscillator. The semiconductor integrated circuit is equipped with the digitally controlled oscillator. The digitally controlled oscillator comprises oscillation transistors and a resonant circuit. The resonant circuit comprises inductances, a frequency coarse-tuning variable capacitor array and a frequency fine-tuning variable capacitor array. The frequency coarse-tuning variable capacitor array comprises a plurality of coarse-tuning capacitor unit cells. The frequency fine-tuning variable capacitor array comprises a plurality of fine-tuning capacitor unit cells. The capacitance values of the coarse-tuning capacitor unit cells of the frequency coarse-tuning variable capacitor array are set in accordance with a binary weight 2M?1.

Abstract: A level converter level-converts an oscillation output signal of a reference frequency oscillator and supplies the level-converted signal to a phase comparator of a PLL/fractional synthesizer for controlling an oscillation frequency of an RF transmission voltage-controlled oscillator. The level converter includes a self-bias type voltage amplifier which amplifies a reference frequency signal of the reference frequency oscillator. The self-bias type voltage amplifier includes a coupling capacitor, an amplifying transistor, a load and a bias element and suppresses a variation in the level of each harmonic component even though an external power supply voltage varies.

Abstract: In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.

Abstract: In a communication semiconductor integrated circuit device using offset PLL architectures and including an oscillator circuit and a frequency divider circuit generating an intermediate frequency signal, the oscillator circuit includes an oscillator, a programmable frequency divider which frequency-divides the oscillation signal in accordance with frequency division information, a phase comparator detecting a phase difference between an output signal of the programmable frequency divider and a reference signal, and a frequency control unit for outputting a signal indicative of the phase difference and controlling the oscillation frequency of the oscillator, wherein a frequency division ratio generator circuit generates an integer part I and a fraction part F/G based on band information concerning the use frequency band and mode information along with channel information and for producing the frequency division ratio information to thereby give it to the programmable frequency divider.

Abstract: In a communication semiconductor integrated circuit device using offset PLL architectures and including an oscillator circuit and a frequency divider circuit generating an intermediate frequency signal, the oscillator circuit includes an oscillator, a programmable frequency divider which frequency-divides the oscillation signal in accordance with frequency division information, a phase comparator detecting a phase difference between an output signal of the programmable frequency divider and a reference signal, and a frequency control unit for outputting a signal indicative of the phase difference and controlling the oscillation frequency of the oscillator, wherein a frequency division ratio generator circuit generates an integer part I and a fraction part F/G based on band information concerning the use frequency band and mode information along with channel information and for producing the frequency division ratio information to thereby give it to the programmable frequency divider.

Abstract: The present invention provides a semiconductor integrated circuit for communication (RF IC) operable in a mode for receiving a received signal subjected to phase modulation and amplitude modulation and a mode for receiving a received signal subjected only to phase modulation. In the semiconductor integrated circuit for communication, a frequency band of a loop filter in a PLL circuit is switched and set so as to become large in a reception mode and become small in a transmission mode.