Patents by Inventor Toshiyuki Kouchi
Toshiyuki Kouchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230352093Abstract: According to one embodiment, a semiconductor memory device includes a first circuit configured to receive first bit data of an input signal, store, in a first latch circuit, first data based on the first bit data and a reference voltage, and output a first signal based on the first data, and a second circuit configured to receive second bit data of the input signal, store, in a second latch circuit, second data based on the second bit data and the reference voltage, and output a second signal based on the second data. The first circuit is configured to set the first latch circuit in a reset state based on the second signal. The second circuit is configured compare the second bit data and the reference voltage based on the first data and set the second latch circuit in a reset state based on the first signal.Type: ApplicationFiled: March 3, 2023Publication date: November 2, 2023Applicant: Kioxia CorporationInventors: Junya MATSUNO, Yasuhiro HIRASHIMA, Toshiyuki KOUCHI
-
Publication number: 20230326535Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.Type: ApplicationFiled: June 13, 2023Publication date: October 12, 2023Applicant: KIOXIA CORPORATIONInventors: Shinya OKUNO, Shigeki NAGASAKA, Toshiyuki KOUCHI
-
Patent number: 11715529Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.Type: GrantFiled: March 8, 2022Date of Patent: August 1, 2023Assignee: KIOXIA CORPORATIONInventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
-
Publication number: 20220189563Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.Type: ApplicationFiled: March 8, 2022Publication date: June 16, 2022Applicant: KIOXIA CORPORATIONInventors: Shinya OKUNO, Shigeki NAGASAKA, Toshiyuki KOUCHI
-
Patent number: 11295821Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.Type: GrantFiled: January 28, 2021Date of Patent: April 5, 2022Assignee: KIOXIA CORPORATIONInventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
-
Publication number: 20210151114Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.Type: ApplicationFiled: January 28, 2021Publication date: May 20, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Shinya OKUNO, Shigeki NAGASAKA, Toshiyuki KOUCHI
-
Patent number: 10950314Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.Type: GrantFiled: March 12, 2020Date of Patent: March 16, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
-
Publication number: 20200211659Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.Type: ApplicationFiled: March 12, 2020Publication date: July 2, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Shinya OKUNO, Shigeki NAGASAKA, Toshiyuki KOUCHI
-
Patent number: 10636499Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.Type: GrantFiled: May 24, 2019Date of Patent: April 28, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
-
Patent number: 10438670Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.Type: GrantFiled: June 15, 2018Date of Patent: October 8, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
-
Patent number: 10438929Abstract: According to one embodiment, M (M represents an integer of 2 or larger) semiconductor chips and through electrodes for N (N represents an integer of 2 or larger) channels are provided. The M semiconductor chips are stacked in sequence. The through electrodes are embedded in the semiconductor chips to connect electrically the semiconductor chips in the direction of stacking. The connection destination of the through electrodes are exchanged between one or more upper and lower layers of the semiconductor chips.Type: GrantFiled: September 17, 2014Date of Patent: October 8, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Toshiyuki Kouchi, Masaru Koyanagi
-
Patent number: 10423666Abstract: A semiconductor device that writes, into respective memory spaces of a plurality of separate memories constituting a search memory mat, an entry address corresponding to key data to be written. In this semiconductor device, pieces of divided data are assigned respectively to the separate memories, and, by employing each divided data as an address, entry addresses corresponding to the divided data are written sequentially into memory spaces specified by memory addresses of the separate memories (first writing process). In this first writing process, if another entry address is already written in an accessed memory space, no entry address is written into that memory space. If an entry address corresponding to a single one of the plurality of pieces of divided data is successfully written into a memory space, the first writing process is ended. Second write processing to a verification memory may also be performed. Key data may be written to a backup memory when a whole collision occurs.Type: GrantFiled: April 18, 2016Date of Patent: September 24, 2019Assignee: NAGASE & CO., LTD.Inventors: Masato Nishizawa, Kaoru Kobayashi, Kanji Otsuka, Yoichi Sato, Toshiyuki Kouchi, Minoru Uwai
-
Publication number: 20190279727Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.Type: ApplicationFiled: May 24, 2019Publication date: September 12, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Shinya OKUNO, Shigeki NAGASAKA, Toshiyuki KOUCHI
-
Patent number: 10381092Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.Type: GrantFiled: June 15, 2018Date of Patent: August 13, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
-
Patent number: 10204900Abstract: A semiconductor device includes a first circuit configured to generate a current corresponding to the input signal, a second circuit configured to generate a voltage corresponding to the current generated by the first circuit, a constant current source, a transistor that includes a drain terminal receiving a current from the constant current source and a gate terminal to which the voltage corresponding to the current generated by the first circuit is applied, and an amplification circuit configured to amplify a difference voltage between a drain voltage of the transistor and a reference voltage and output the amplified difference voltage as an output signal corresponding to the input signal.Type: GrantFiled: August 8, 2017Date of Patent: February 12, 2019Assignee: Toshiba Memory CorporationInventors: Toshiyuki Kouchi, Shinya Okuno
-
Patent number: 10180692Abstract: A semiconductor device of one embodiment includes semiconductor chips. While the semiconductor device is receiving a power supply and a chip enable signal which is negated, all external terminals of the semiconductor chips are at the same logic level.Type: GrantFiled: August 24, 2015Date of Patent: January 15, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventor: Toshiyuki Kouchi
-
Publication number: 20180294038Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.Type: ApplicationFiled: June 15, 2018Publication date: October 11, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Shinya OKUNO, Shigeki NAGASAKA, Toshiyuki KOUCHI
-
Patent number: 10026485Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.Type: GrantFiled: August 7, 2017Date of Patent: July 17, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shinya Okuno, Shigeki Nagasaka, Toshiyuki Kouchi
-
Publication number: 20180129756Abstract: Disclosed is a semiconductor device that writes, into respective memory spaces of a plurality of divisional memories constituting a search memory mat, an entry address corresponding to key data to be written. In this semiconductor device, pieces of divisional data are assigned respectively to the divisional memories, and, by employing each divisional data as an address, an entry address corresponding to said divisional data is written sequentially into a memory space specified by a memory address of each said divisional memory (first writing process). In this first writing process, if another entry address is already written in an accessed memory space, no entry address is written into that memory space. If an entry address corresponding to one of the plurality of pieces of divisional data is successfully written into a memory space, the first writing process is ended.Type: ApplicationFiled: April 18, 2016Publication date: May 10, 2018Applicant: NAGASE & CO., LTD.Inventors: Masato NISHIZAWA, Kaoru KOBAYASHI, Kanji OTSUKA, Yoichi SATO, Toshiyuki KOUCHI, Minoru UWAI
-
Publication number: 20180053759Abstract: A semiconductor device includes a first circuit configured to generate a current corresponding to the input signal, a second circuit configured to generate a voltage corresponding to the current generated by the first circuit, a constant current source, a transistor that includes a drain terminal receiving a current from the constant current source and a gate terminal to which the voltage corresponding to the current generated by the first circuit is applied, and an amplification circuit configured to amplify a difference voltage between a drain voltage of the transistor and a reference voltage and output the amplified difference voltage as an output signal corresponding to the input signal.Type: ApplicationFiled: August 8, 2017Publication date: February 22, 2018Inventors: Toshiyuki KOUCHI, Shinya OKUNO