Abstract: A clock non-synchronous type circuit performs data read operation on the basis of a read control signal. After a lapse of a predetermined delay time, read data is read out from the clock non-synchronous type circuit. The read data is latched in selected one of N latch circuits. A latch circuit is selected on the basis of a control signal instead of a clock signal. The control signal represents that read data is output from the clock non-synchronous type circuit, and hence a latch circuit is always selected after read data is output.

Abstract: A region of a memory macro function block is divided into memory core function block and interface function block regions. The interface function block includes a test circuit, a command decoder for a test, an address decoder for the test, a memory core input/output circuit which inputs a command and address into the memory core function block and transmits/receives data with the memory core function block, a configuration memory block in which information of a memory capacity of the memory core function block and configuration of a memory core is stored, and a configuration memory block which controls a data path and address path of the memory core function block based on the stored information.

Abstract: A clock non-synchronous type circuit performs data read operation on the basis of a read control signal. After a lapse of a predetermined delay time, read data is read out from the clock non-synchronous type circuit. The read data is latched in selected one of N latch circuits. A latch circuit is selected on the basis of a control signal instead of a clock signal. The control signal represents that read data is output from the clock non-synchronous type circuit, and hence a latch circuit is always selected after read data is output.

Abstract: A logic in DRAM LSI is disclosed, which comprises a plurality of DRAM circuits, a control circuit that receives a test control signal to perform a test control in which the plurality of RAM circuits are tested while the access to the plurality of DRAM circuits is subsequently changed for each row, an input selector that is controlled by the control circuit and inputs a DRAM macro signal to the plurality of DRAM circuits at the time of a test, and an output selector that is controlled by the control circuit, and outputs output signals of the plurality of DRAM circuits sequentially to a macro output terminal at the time of the test. According to the DRAM integrated LSI, a test time required to test the plurality of DRAM circuits integrated in the LSI is shortened. Moreover, data that is read from the plurality of DRAM circuits is transferred in a high speed.