Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of stacked first chips and a second chip. The second chip outputs a first signal to the first chips. The first chip outputs status information at timing based on the received first signal. The first chip shifts the received first signal and outputs the shifted first signal to the first chip of a next stage in synchronization with the first clock signal. The second chip receives a plurality of status information output in a serial manner from the first chips.

Abstract: According to one embodiment, M (M represents an integer of 2 or larger) semiconductor chips and through electrodes for N (N represents an integer of 2 or larger) channels are provided. The M semiconductor chips are stacked in sequence. The through electrodes are embedded in the semiconductor chips to connect electrically the semiconductor chips in the direction of stacking. The connection destination of the through electrodes are exchanged between one or more upper and lower layers of the semiconductor chips.

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip outputs a first signal by a first bus width and includes a first via which transfers the first signal. The second semiconductor chip receives, by the first bus width, the first signal transferred through the first via.

Abstract: According to one embodiment, a semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed closer to the input/output circuit than the first FIFO.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip outputs a first signal by a first bus width and includes a first via which transfers the first signal. The second semiconductor chip receives, by the first bus width, the first signal transferred through the first via.

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed closer to the input/output circuit than the first FIFO.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of stacked first chips and a second chip. The second chip outputs a first signal to the first chips. The first chip outputs status information at timing based on the received first signal. The first chip shifts the received first signal and outputs the shifted first signal to the first chip of a next stage in synchronization with the first clock signal. The second chip receives a plurality of status information output in a serial manner from the first chips.

Abstract: A semiconductor device of one embodiment includes semiconductor chips. While the semiconductor device is receiving a power supply and a chip enable signal which is negated, all external terminals of the semiconductor chips are at the same logic level.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a clock signal transmission path configured to transmit a clock signal and a data transmission path configured to transmit data. The clock signal transmission path has a first and a second clock signal transmission line configured to transmit a clock signal and a complementary clock signal. The data transmission path has a first and a second data transmission line configured to transmit data and complementary data. Each transmission path has an amplifier circuit of each signal and a level adjustment circuit for reducing amplitude of output from the amplifier circuit.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a clock signal transmission path configured to transmit a clock signal and a data transmission path configured to transmit data. The clock signal transmission path has a first and a second clock signal transmission line configured to transmit a clock signal and a complementary clock signal. The data transmission path has a first and a second data transmission line configured to transmit data and complementary data. Each transmission path has an amplifier circuit of each signal and a level adjustment circuit for reducing amplitude of output from the amplifier circuit.

Abstract: A semiconductor memory device includes first and second driving transistors; first and second load transistors; and first and second transmission transistors. Their respective drain diffusion layers of the transistors are isolated from one another. The semiconductor memory device also includes a bit cell in which the first and second driving transistors, the first and second load transistors, and the first and second transmission transistors are arranged; a first wiring for connecting their respective drains of the first driving transistor, the first load transistor, and the first transmission transistor; and a second wiring for connecting their respective drains of the second driving transistor, the second load transistor, and the second transmission transistor.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a memory cell array includes data storage units which are arranged at intersections of word lines and bit lines and hold data, a reversing circuit which logically reverses held data stored in the data storage units, and a flag bit column which stores, for each row, a flag for identifying presence/absence of logic reversal of data stored in the data storage units.

Abstract: A semiconductor memory device includes first and second driving transistors; first and second load transistors; and first and second transmission transistors. Their respective drain diffusion layers of the transistors are isolated from one another. The semiconductor memory device also includes a bit cell in which the first and second driving transistors, the first and second load transistors, and the first and second transmission transistors are arranged; a first wiring for connecting their respective drains of the first driving transistor, the first load transistor, and the first transmission transistor; and a second wiring for connecting their respective drains of the second driving transistor, the second load transistor, and the second transmission transistor.

Abstract: First and second anti-fuse elements are provided for storing 1-bit data. A program voltage generating circuit generates a programming voltage and applies it to the first and second anti-fuse elements. A read voltage generating circuit generates a readout voltage and applies it to the first and second anti-fuse elements. First and second transistors are inserted between the first and second anti-fuse elements and a ground potential node, and are respectively turned on by first and second select signals during the programming period. A switch element is connected between the first and the second transistors. The switch element is turned off during the programming period, and turned on during the readout period. A sense amplifier is connected to the switch element in order to sense the data read out from the first and the second anti-fuse elements.

Abstract: First and second anti-fuse elements are provided for storing 1-bit data. A program voltage generating circuit generates a programming voltage and applies it to the first and second anti-fuse elements. A read voltage generating circuit generates a readout voltage and applies it to the first and second anti-fuse elements. First and second transistors are inserted between the first and second anti-fuse elements and a ground potential node, and are respectively turned on by first and second select signals during the programming period. A switch element is connected between the first and the second transistors. The switch element is turned off during the programming period, and turned on during the readout period. A sense amplifier is connected to the switch element in order to sense the data read out from the first and the second anti-fuse elements.

Abstract: A semiconductor integrated circuit including a region of a memory macro function block is divided into memory core function block and interface function block regions. The interface function block includes a test circuit, a command decoder for a test, an address decoder for the test, a memory core input/output circuit which inputs a command and address into the memory core function block and transmits!receives data with the memory core function block, a configuration memory block in which information of a memory capacity of the memory core function block and configuration of a memory core is stored, and a configuration memory block which controls a data path and address path of the memory core function block based on the stored information.

Abstract: A logic in DRAM LSI is disclosed, which comprises a plurality of DRAM circuits, a control circuit that receives a test control signal to perform a test control in which the plurality of RAM circuits are tested while the access to the plurality of DRAM circuits is subsequently changed for each row, an input selector that is controlled by the control circuit and inputs a DRAM macro signal to the plurality of DRAM circuits at the time of a test, and an output selector that is controlled by the control circuit, and outputs output signals of the plurality of DRAM circuits sequentially to a macro output terminal at the time of the test. According to the DRAM integrated LSI, a test time required to test the plurality of DRAM circuits integrated in the LSI is shortened. Moreover, data that is read from the plurality of DRAM circuits is transferred in a high speed.