Patents by Inventor Trung T. Doan
Trung T. Doan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8066551Abstract: A retaining ring can be shaped by machining or lapping the bottom surface of the ring to form a shaped profile in the bottom surface. The bottom surface of the retaining ring can include flat, sloped and curved portions. The lapping can be performed using a machine that dedicated for use in lapping the bottom surface of retaining rings. During the lapping the ring can be permitted to rotate freely about an axis of the ring. The bottom surface of the retaining ring can have curved or flat portions.Type: GrantFiled: April 18, 2011Date of Patent: November 29, 2011Assignee: Applied Materials, Inc.Inventors: Hung Chih Chen, Steven M. Zuniga, Charles C. Garretson, Douglas R. McAllister, Jian Lin, Stacy Meyer, Sidney P. Huey, Jeonghoon Oh, Trung T. Doan, Jeffrey P. Schmidt, Martin S. Wohlert, Kerry F. Hughes, James C. Wang, Danny Cam Toan Lu, Romain Beau De Lamenie, Venkata R. Balagani, Aden Martin Allen, Michael Jon Fong
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Publication number: 20110284866Abstract: A light emitting diode (LED) device having a substantially conformal wavelength-converting layer for producing uniform white light and a method of making said LED at both the wafer and individual die levels are provided. The LED device includes a metal substrate, a p-type semiconductor coupled to the metal substrate, an active region coupled to the p-type semiconductor, an n-type semiconductor coupled to the active region, and a wavelength converting layer coupled to the n-type semiconductor.Type: ApplicationFiled: July 26, 2011Publication date: November 24, 2011Inventors: CHUONG A. TRAN, Trung T. Doan, Jui-Kang Yen, Yung-Wei Chen
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Patent number: 8034716Abstract: Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: GrantFiled: May 1, 2009Date of Patent: October 11, 2011Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung T. Doan, Raymond A. Turi, Graham R. Wolstenholme
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Patent number: 8012774Abstract: A light emitting diode (LED) device having a substantially conformal wavelength-converting layer for producing uniform white light and a method of making said LED at both the wafer and individual die levels are provided. The LED device includes a metal substrate, a p-type semiconductor coupled to the metal substrate, an active region coupled to the p-type semiconductor, an n-type semiconductor coupled to the active region, and a wavelength-converting layer coupled to the n-type semiconductor.Type: GrantFiled: September 8, 2006Date of Patent: September 6, 2011Assignee: SemiLEDs Optoelectronics Co., Ltd.Inventors: Chuong A. Tran, Trung T. Doan, Jui-Kang Yen, Yung-Wei Chen
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Publication number: 20110195639Abstract: A retaining ring can be shaped by machining or lapping the bottom surface of the ring to form a shaped profile in the bottom surface. The bottom surface of the retaining ring can include flat, sloped and curved portions. The lapping can be performed using a machine that dedicated for use in lapping the bottom surface of retaining rings. During the lapping the ring can be permitted to rotate freely about an axis of the ring. The bottom surface of the retaining ring can have curved or flat portions.Type: ApplicationFiled: April 18, 2011Publication date: August 11, 2011Inventors: Hung Chih Chen, Steven M. Zuniga, Charles C. Garretson, Douglas R. McAllister, Jian Lin, Stacy Meyer, Sidney P. Huey, Jeonghoon Oh, Trung T. Doan, Jeffrey Schmidt, Martin S. Wohlert, Kerry F. Hughes, James C. Wang, Danny Cam Toan Lu, Romain Beau De Lamenie, Venkata R. Balagani, Aden Martin Allen, Michael Jon Fong
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Publication number: 20110163416Abstract: The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 ?.Type: ApplicationFiled: March 14, 2011Publication date: July 7, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Lingyi A. Zheng, Trung T. Doan, Lyle D. Breiner, Er-Xuan Ping, Kevin L. Beaman, Ronald A. Weimer, Cem Basceri, David J. Kubista
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Patent number: 7964436Abstract: The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (GexSe1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with the metal. The chalcogenide glass doped with the metal can be used to store data in a memory device. Advantageously, the systems and methods co-sputter the metal and the chalcogenide glass and allow for relatively precise and efficient control of a constituent ratio between the doping metal and the chalcogenide glass. Further advantageously, the systems and methods enable the doping of the chalcogenide glass with a relatively high degree of uniformity over the depth of the formed layer of chalcogenide glass and the metal. Also, the systems and methods allow a metal concentration to be varied in a controlled manner along the thin film depth.Type: GrantFiled: October 10, 2008Date of Patent: June 21, 2011Assignee: Round Rock Research, LLCInventors: Jiutao Li, Allen McTeer, Gregory Herdt, Trung T. Doan
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Patent number: 7935950Abstract: An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of programming the same are disclosed. Such memory devices include a lower electrode including non-parallel sidewalls. An insulative material overlies the lower electrode such that an upper surface of the lower electrode is exposed. In one embodiment, the insulative material and lower electrode may have a co-planar upper surface. In another embodiment, an upper surface of the lower electrode is within a recess in the insulative material. A chalcogenide material and an upper electrode are formed over the upper surface of the lower electrode. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.Type: GrantFiled: August 2, 2007Date of Patent: May 3, 2011Assignee: Round Rock Research, LLCInventors: Trung T. Doan, D. Mark Durcan, Brent D. Gilgen
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Patent number: 7927190Abstract: A retaining ring can be shaped by machining or lapping the bottom surface of the ring to form a shaped profile in the bottom surface. The bottom surface of the retaining ring can include flat, sloped and curved portions. The lapping can be performed using a machine that dedicated for use in lapping the bottom surface of retaining rings. During the lapping the ring can be permitted to rotate freely about an axis of the ring. The bottom surface of the retaining ring can have curved or flat portions.Type: GrantFiled: March 17, 2008Date of Patent: April 19, 2011Assignee: Applied Materials, Inc.Inventors: Hung Chih Chen, Steven M. Zuniga, Charles C. Garretson, Douglas R. McAllister, Jian Lin, Stacy Meyer, Sidney P. Huey, Jeonghoon Oh, Trung T. Doan, Jeffrey Schmidt, Martin S. Wohlert, Kerry F. Hughes, James C. Wang, Danny Cam Toan Lu, Romain Beau De Lamenie, Venkata R. Balagani, Aden Martin Allen, Michael Jon Fong
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Patent number: 7906393Abstract: The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 ?.Type: GrantFiled: January 28, 2004Date of Patent: March 15, 2011Assignee: Micron Technology, Inc.Inventors: Lingyi A. Zheng, Trung T. Doan, Lyle D. Breiner, Er-Xuan Ping, Kevin L. Beaman, Ronald A. Weimer, Cem Basceri, David J. Kubista
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Patent number: 7871934Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.Type: GrantFiled: August 20, 2007Date of Patent: January 18, 2011Assignee: Round Rock Research, LLCInventors: Charles H. Dennison, Trung T. Doan
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Publication number: 20100282164Abstract: The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.Type: ApplicationFiled: July 20, 2010Publication date: November 11, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Kevin L. Beaman, Trung T. Doan, Lyle D. Breiner, Ronald A. Weimer, Er-Xuan Ping, David J. Kubista, Cem Basceri, Lingyi A. Zheng
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Patent number: 7807503Abstract: A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a second, opposing surface thereof. Each of the first and second pluralities of bond pads includes an under-bump metallization (UBM) layer. The singulated semiconductor die is disposed on a semiconductor die site of a semiconductor wafer and a first plurality of conductive bumps electrically couples the first plurality of bond pads of the singulated semiconductor die with a first set of bond pads formed on the semiconductor die site. A second plurality of conductive bumps is disposed on a second set of bond pads of the semiconductor die site. A third plurality of conductive bumps is disposed on the singulated semiconductor die's second plurality of bond pads. The second and third pluralities of conductive bumps are configured for electrical interconnection with an external device.Type: GrantFiled: August 19, 2008Date of Patent: October 5, 2010Assignee: Micron Technology, Inc.Inventor: Trung T. Doan
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Patent number: 7771537Abstract: The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in a deposition process, e.g., in depositing a heat-reflective material via CVD. One exemplary embodiment provides a method that involves monitoring a first temperature outside the deposition chamber and a second temperature inside the deposition chamber. An internal temperature in the deposition chamber can be increased in accordance with a ramp profile by (a) comparing a control temperature to a target temperature, and (b) selectively delivering heat to the deposition chamber in response to a result of the comparison. The target temperature may be determined in accordance with the ramp profile, but the control temperature in one implementation alternates between the first temperature and the second temperature.Type: GrantFiled: May 4, 2006Date of Patent: August 10, 2010Assignee: Micron Technology, Inc.Inventors: Kevin L. Beaman, Trung T. Doan, Lyle D. Breiner, Ronald A. Weimer, Er-Xuan Ping, David J. Kubista, Cem Basceri, Lingyi A. Zheng
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Publication number: 20100102433Abstract: A chip-scale or wafer-level package, having passivation layers on substantially all surfaces thereof to form a hermetically sealed package, is provided. The package may be formed by disposing a first passivation layer on the passive or back side surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.Type: ApplicationFiled: December 30, 2009Publication date: April 29, 2010Applicant: MICRON TECHNOLOGY, INC.Inventor: Trung T. Doan
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Patent number: 7656012Abstract: A chip-scale or wafer-level-package, having passivation layers on substantially all surfaces thereof to form a hermetically sealed-package, is provided. The package may be formed by disposing a first passivation layer on the passive or backside surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.Type: GrantFiled: April 21, 2006Date of Patent: February 2, 2010Assignee: Micron Technology, Inc.Inventor: Trung T. Doan
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Publication number: 20100019388Abstract: A process for forming vertical contacts in the manufacture of integrated circuits and devices eliminating the need for precise mask alignment and allowing the etching of the contact hole controlled independent of the etching of the interconnect trough that may be repeated during the formation of multilevel integrated circuits. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole.Type: ApplicationFiled: September 23, 2009Publication date: January 28, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Charles H. Dennison, Trung T. Doan
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Patent number: 7647886Abstract: Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers are disclosed herein. In one embodiment, the system includes a gas phase reaction chamber, a first exhaust line coupled to the reaction chamber, first and second traps each in fluid communication with the first exhaust line, and a vacuum pump coupled to the first exhaust line to remove gases from the reaction chamber. The first and second traps are operable independently to individually and/or jointly collect byproducts from the reaction chamber. It is emphasized that this Abstract is provided to comply with the rules requiring an abstract. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: GrantFiled: October 15, 2003Date of Patent: January 19, 2010Assignee: Micron Technology, Inc.Inventors: David J. Kubista, Trung T. Doan, Lyle D. Breiner, Ronald A. Weimer, Kevin L. Beaman, Er-Xuan Ping, Lingyi A. Zheng, Cem Basceri
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Publication number: 20090311843Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.Type: ApplicationFiled: August 25, 2009Publication date: December 17, 2009Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez, Er-Xuan Ping
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Patent number: 7625694Abstract: Disclosed herein are techniques for using diblock copolymer (DBCP) films as etch masks to form small dots or holes in integrated circuit layers. In an embodiment, the DBCP film is deposited on the circuit layer to be etched. Then the DCBP film is confined to define an area of interest in the DCBP film in which hexagonal domains will eventually be formed. Such confinement can constitute masking and exposing the DCBP film using photolithographic techniques. Such masking preferably incorporates knowledge of the domain spacing and/or grain size of the to-be-formed domains in the area of interest to ensure that a predictable number and/or orientation of the domains will result in the area of interest, although this is not strictly necessary in all useful embodiments. Domains are then formed in the area of interest in the DBCP film which comprises a hexagonal array of cylindrical domains in a matrix. The film is then treated (e.g.Type: GrantFiled: May 6, 2004Date of Patent: December 1, 2009Assignee: Micron Technology, Inc.Inventors: Eugene P. Marsh, Daryl C. New, Trung T. Doan