Patents by Inventor Trung T. Doan
Trung T. Doan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7625795Abstract: Container capacitor structure and method of construction. An etch mask and etch are used to expose portions of an exterior surface of an electrode (“bottom electrodes”) of the structure. The etch provides a recess between proximal pairs of container capacitor structures, which is available for forming additional capacitance. A capacitor dielectric and top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Surface area common to both the first electrode and second electrodes is increased over using only the interior surface, providing additional capacitance without decreasing spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.Type: GrantFiled: September 1, 2005Date of Patent: December 1, 2009Assignee: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez, Er-Xuan Ping
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Patent number: 7588677Abstract: A method and apparatus for removing conductive material from a microelectronic substrate. In one embodiment, the method can include engaging a microelectronic substrate with a polishing surface of a polishing pad, electrically coupling a conductive material of the microelectronic substrate to a source of electrical potential, and oxidizing at least a portion of the conductive material by passing an electrical current through the conductive material from the source of electrical potential. For example, the method can include positioning first and second electrodes apart from a face surface of the microelectronic substrate and disposing an electrolytic fluid between the face surface and the electrodes with the electrodes in fluid communication with the electrolytic fluid. The method can further include removing the portion of conductive material from the microelectronic substrate by moving at least one of the microelectronic and the polishing pad relative to the other.Type: GrantFiled: June 12, 2006Date of Patent: September 15, 2009Assignee: Micron Technology, Inc.Inventors: Whonchee Lee, Scott G. Meikle, Scott E. Moore, Trung T. Doan
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Patent number: 7579235Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.Type: GrantFiled: October 10, 2006Date of Patent: August 25, 2009Assignee: Micron Technology, Inc.Inventors: D. Mark Durcan, Trung T. Doan, Roger R. Lee, Fernando Gonzalez, Er-Xuan Ping
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Patent number: 7569485Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.Type: GrantFiled: August 19, 2004Date of Patent: August 4, 2009Assignee: Micron Technology, Inc.Inventors: Charles H Dennison, Trung T. Doan
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Patent number: 7530153Abstract: Techniques for attaching a retaining ring to a carrier head so that the bottom surface of the retaining ring is orthogonal to a central rotational axis of the carrier head are described.Type: GrantFiled: September 21, 2005Date of Patent: May 12, 2009Assignee: Applied Materials, Inc.Inventors: Trung T. Doan, Jeffrey Schmidt, Douglas R. McAllister, Stacy Meyer
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Publication number: 20090098717Abstract: The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (GexSe1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with the metal. The chalcogenide glass doped with the metal can be used to store data in a memory device. Advantageously, the systems and methods co-sputter the metal and the chalcogenide glass and allow for relatively precise and efficient control of a constituent ratio between the doping metal and the chalcogenide glass. Further advantageously, the systems and methods enable the doping of the chalcogenide glass with a relatively high degree of uniformity over the depth of the formed layer of chalcogenide glass and the metal. Also, the systems and methods allow a metal concentration to be varied in a controlled manner along the thin film depth.Type: ApplicationFiled: October 10, 2008Publication date: April 16, 2009Inventors: Jiutao Li, Allen McTeer, Gregory Herdt, Trung T. Doan
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Patent number: 7504008Abstract: In a method of refurbishing a deposition target, a surface of the target is provided in a process zone. An electrical arc is generated in the process zone, and a consumable metal wire is inserted into the process zone to form liquefied metal. A pressurized gas is injected into the process zone to direct the liquefied metal toward the surface of the target to splatter the liquefied metal on the surface, thereby forming a coating having the metal on at least a portion of the surface of the target that exhibits reduced contamination from the environment.Type: GrantFiled: March 12, 2004Date of Patent: March 17, 2009Assignee: Applied Materials, Inc.Inventors: Trung T. Doan, Kenny King-Tai Ngan
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Patent number: 7485961Abstract: A method is disclosed for reducing the effects of buckling, also referred to as cracking or wrinkling in multilayer heterostructures. The present method involves forming a planarization layer superjacent a semiconductor substrate. A barrier film having a structural integrity is formed superjacent the planarization layer. A second layer is formed superjacent the barrier film. The substrate is heated sufficiently to cause the planarization layer to expand according to a first thermal coefficient of expansion, the second layer to expand according to a second thermal coefficient of expansion, and the structural integrity of the barrier film to be maintained. This results in the barrier film isolating the planarization layer from the second layer, thereby preventing the planarization layer and the second layer from interacting during the heating step.Type: GrantFiled: February 9, 2004Date of Patent: February 3, 2009Assignee: Micron Technology, Inc.Inventors: Trung T. Doan, Randhir P. S. Thakur, Yauh-Ching Liu
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Publication number: 20090011540Abstract: A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a second opposing surface thereof. Each of the first and second pluralities of bond pads includes an under-bump metallization (UBM) layer. The singulated semiconductor die is disposed on a semiconductor die site of a semiconductor wafer and a first plurality of conductive bumps electrically couples the first plurality of bond pads of the singulated semiconductor die with a first set of bond pads formed on the semiconductor die site. A second plurality of conductive bumps is disposed on a second set of bond pads of the semiconductor die site. A third plurality of conductive bumps is disposed on the singulated semiconductor die's second plurality of bond pads. The second and third pluralities of conductive bumps are configured for electrical interconnection with an external device.Type: ApplicationFiled: August 19, 2008Publication date: January 8, 2009Applicant: MICRON TECHNOLOGY, INC.Inventor: Trung T. Doan
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Patent number: 7470344Abstract: A method for dispensing a chemical, such as an edge bead removal solvent, onto a semiconductor wafer comprising the steps of dispensing the chemical selectively onto the wafer and applying a suction to the area immediately surrounding the location at which the chemical is dispensed onto the wafer. Preferably, the suction is applied substantially simultaneously with the dispensing of the chemical. One specific version of the invention provides an edge bead removal system wherein suction is applied to the area immediately surrounding the solvent dispensing nozzle to remove dissolved coating material and excess solvent from the wafer. In one aspect of this system, an apparatus for removing the edge bead includes a mechanism for dispensing a solvent selectively onto the edge of the wafer, and a mechanism surrounding the dispensing mechanism for vacuuming excess solvent and dissolved coating material from the edge of the wafer.Type: GrantFiled: August 31, 2000Date of Patent: December 30, 2008Assignee: Micron Technology, Inc.Inventor: Trung T. Doan
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Patent number: 7446393Abstract: The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (GexSe1-x) to be doped with a metal such as silver, copper, or zinc without utilizing an ultraviolet (UV) photodoping step to dope the chalcogenide glass with the metal. The chalcogenide glass doped with the metal can be used to store data in a memory device. Advantageously, the systems and methods co-sputter the metal and the chalcogenide glass and allow for relatively precise and efficient control of a constituent ratio between the doping metal and the chalcogenide glass. Further advantageously, the systems and methods enable the doping of the chalcogenide glass with a relatively high degree of uniformity over the depth of the formed layer of chalcogenide glass and the metal. Also, the systems and methods allow a metal concentration to be varied in a controlled manner along the thin film depth.Type: GrantFiled: February 26, 2007Date of Patent: November 4, 2008Assignee: Micron Technology, Inc.Inventors: Jiutao Li, Allen McTeer, Gregory Herdt, Trung T. Doan
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Patent number: 7422635Abstract: The present disclosure suggests several systems and methods for batch processing of microfeature workpieces, e.g., semiconductor wafers or the like. One exemplary implementation provides a method of depositing a reaction product on each of a batch of workpieces positioned in a process chamber in a spaced-apart relationship. A first gas may be delivered to an elongate first delivery conduit that includes a plurality of outlets spaced along a length of the conduit. A first gas flow may be directed by the outlets to flow into at least one of the process spaces between adjacent workpieces along a first vector that is transverse to the direction in which the workpieces are spaced. A second gas may be delivered to an elongate second delivery conduit that also has outlets spaced along its length. A second gas flow of the second gas may be directed by the outlets to flow into the process spaces along a second vector that is transverse to the first direction.Type: GrantFiled: August 28, 2003Date of Patent: September 9, 2008Assignee: Micron Technology, Inc.Inventors: Lingyi A. Zheng, Trung T. Doan, Lyle D. Breiner, Er-Xuan Ping, Kevin L. Beaman, Ronald A. Weimer, David J. Kubista, Cem Basceri
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Publication number: 20080196833Abstract: A retaining ring can be shaped by machining or lapping the bottom surface of the ring to form a shaped profile in the bottom surface. The bottom surface of the retaining ring can include flat, sloped and curved portions. The lapping can be performed using a machine that dedicated for use in lapping the bottom surface of retaining rings. During the lapping the ring can be permitted to rotate freely about an axis of the ring. The bottom surface of the retaining ring can have curved or flat portions.Type: ApplicationFiled: March 17, 2008Publication date: August 21, 2008Applicant: APPLIED MATERIALS, INC.Inventors: Hung Chih Chen, Steven M. Zuniga, Charles C. Garretson, Douglas R. McAllister, Jian Lin, Stacy Meyer, Sidney P. Huey, Jeonghoon Oh, Trung T. Doan, Jeffrey Schmidt, Martin S. Wohlert, Kerry F. Hughes, James C. Wang, Danny Cam Toan Lu, Romain Beau De Lamenie, Venkata R. Balagani, Aden Martin Allen, Michael Jon Fong
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Patent number: 7413928Abstract: A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a second opposing surface thereof. Each of the first and second pluralities of bond pads includes an under-bump metallization (UBM) layer. The singulated semiconductor die is disposed on a semiconductor die site of a semiconductor wafer and a first plurality of conductive bumps electrically couples the first plurality of bond pads of the singulated semiconductor die with a first set of bond pads formed on the semiconductor die site. A second plurality of conductive bumps is disposed on a second set of bond pads of the semiconductor die site. A third plurality of conductive bumps is disposed on the singulated semiconductor die's second plurality of bond pads. The second and third pluralities of conductive bumps are configured for electrical interconnection with an external device.Type: GrantFiled: July 25, 2006Date of Patent: August 19, 2008Assignee: Micron Technology, Inc.Inventor: Trung T. Doan
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Patent number: 7344434Abstract: A retaining ring can be shaped by machining or lapping the bottom surface of the ring to form a shaped profile in the bottom surface. The bottom surface of the retaining ring can include flat, sloped and curved portions. The lapping can be performed using a machine that dedicated for use in lapping the bottom surface of retaining rings. During the lapping the ring can be permitted to rotate freely about an axis of the ring. The bottom surface of the retaining ring can have curved or flat portions.Type: GrantFiled: November 12, 2004Date of Patent: March 18, 2008Assignee: Applied Materials, Inc.Inventors: Hung Chih Chen, Steven M. Zuniga, Charles C. Garretson, Douglas R. McAllister, Stacy Meyer, Trung T. Doan, Daniel Cam Toan Lu, Romain Beau De Lamenie, Venkata R. Balagani, Aden Martin Allen, Michael Jon Fong
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Patent number: 7344755Abstract: The present disclosure provides methods and apparatus that may be used to process microfeature workpieces, e.g., semiconductor wafers. Some aspects have particular utility in depositing TiN in a batch process. One implementation involves pretreating a surface of a process chamber by contemporaneously introducing first and second pretreatment precursors (e.g., TiCl4 and NH3) to deposit a pretreatment material on a the chamber surface. After the pretreatment, the first microfeature workpiece may be placed in the chamber and TiN may be deposited on the microfeature workpiece by alternately introducing quantities of first and second deposition precursors.Type: GrantFiled: August 21, 2003Date of Patent: March 18, 2008Assignee: Micron Technology, Inc.Inventors: Kevin L. Beaman, Ronald A. Weimer, Lyle D. Breiner, Er-Xuan Ping, Trung T. Doan, Cem Basceri, David J. Kubista, Lingyi A. Zheng
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Patent number: 7323230Abstract: A coated aluminum component for a substrate processing chamber comprises an aluminum component having a surface; a first aluminum oxide layer formed on the surface of the aluminum component, the aluminum oxide layer having a surface comprising penetrating surface features; and a second aluminum oxide layer on the first aluminum oxide layer, the second aluminum oxide layer substantially completely filling the penetrating surface features of the first aluminum oxide layer. A method of forming the coated aluminum component is also described.Type: GrantFiled: August 2, 2004Date of Patent: January 29, 2008Assignee: Applied Materials, Inc.Inventors: Trung T. Doan, Kenny King-Tai Ngan
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Patent number: 7315082Abstract: A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured, is disclosed. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.Type: GrantFiled: May 22, 2003Date of Patent: January 1, 2008Assignee: Micron Technology, Inc.Inventors: Charles H. Dennison, Trung T. Doan
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Patent number: 7282447Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The process may be repeated during the formation of multilevel metal integrated circuits.Type: GrantFiled: August 19, 2004Date of Patent: October 16, 2007Assignee: Micron Technology, Inc.Inventors: Charles H Dennison, Trung T. Doan
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Patent number: 7282440Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated during the formation of multilevel metal integrated circuits.Type: GrantFiled: May 1, 2002Date of Patent: October 16, 2007Assignee: Micron Technology, Inc.Inventors: Charles H. Dennison, Trung T. Doan