Patents by Inventor Tsukasa Azuma

Tsukasa Azuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5998100
    Abstract: A fabrication process includes a step of providing a substrate to be fabricated. A multi-layer antireflective layer is then formed on the substrate. A patterned resist having a thickness less than 850 nanometers is formed on the multi-layer antireflective layer and the substrate is fabricated using the patterned resist as a mask.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: December 7, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsukasa Azuma, Tokuhisa Ohiwa, Tetsuo Matsuda, David M. Dobuzinsky, Katsuya Okumura
  • Patent number: 5879863
    Abstract: Disclosed is a method of forming a pattern, comprising the steps of forming an underlying film on a semiconductor substrate, bringing a vapor of a neutralizer, which generates an acid upon exposure to light, into contact with the surface of the underlying film so as to form a primer layer, coating the primer layer with a chemical amplification resist, and selectively exposing the resist layer to light, followed by developing to form a resist pattern.
    Type: Grant
    Filed: January 22, 1997
    Date of Patent: March 9, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsukasa Azuma, Masaki Narita, Katsuya Okumura
  • Patent number: 5879853
    Abstract: This invention relates to a top antireflective layer (TAR) which is preferably transparent to some extent and has high-etch resistance and low reflectivity at the photoresist/TAR interface. The TAR also significantly reduces CD variation in exposed photoresist film. The TAR of the present invention comprises an indanone or glutarimide copolymer, a solvent, and an additive sensitizer having an orthodiazonaphthoquinone structure. The present invention is also related to a process of forming a semiconductor by applying a photoresist layer to the surface of a substrate, forming a top antireflection layer on the photoresist layer, and selectively exposing the substrate to ultraviolet light, wherein the TAR comprises an indanone or glutarimide copolymer, a solvent, and an additive sensitizer with an orthodiazonaphthoquinone structure.
    Type: Grant
    Filed: January 18, 1996
    Date of Patent: March 9, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsukasa Azuma
  • Patent number: 5866303
    Abstract: A semiconductor device is fabricated by the steps of coating an underlayer formed on a semiconductor substrate with chemically amplified resist, exposing the resist to light, bringing the resist into contact with an alkaline developing solution with applying a magnetic field to the alkaline developing solution for conducting development to form a resist pattern, and etching the underlayer on the semiconductor substrate using the resist pattern as a mask.
    Type: Grant
    Filed: October 15, 1997
    Date of Patent: February 2, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsukasa Azuma
  • Patent number: 5815247
    Abstract: A system and method of avoiding pattern shortening without resorting to generating a mask with a bias solve the direction dependent differences in exposure behavior in photolithography processes in the manufacture of semiconductor devices. Instead of designing a biased mask to solve the exposure problem, the pattern shortening effect is avoided by influencing the exposure process itself. By using an off axis illumination technique, the exposure is separated into different directions. In one embodiment, off axis illumination is applied in combination with special dipole apertures (i.e., two openings). The exposure is done in two or more parts, whereby the aperture is twisted between exposures. In another embodiment, off axis illumination is used in combination with special polarizer apertures. As with the first embodiment, the exposure is done in two or more parts, but in this case with differently polarized light.
    Type: Grant
    Filed: September 21, 1995
    Date of Patent: September 29, 1998
    Assignees: Siemens Aktiengesellschaft, Kabushiki Kaisha Toshiba
    Inventors: Bernhard Poschenrieder, Takashi Sato, Tsukasa Azuma
  • Patent number: 5759746
    Abstract: A fabrication process includes a step of providing a substrate to be fabricated. A multi-layer antireflective layer is then formed on the substrate. A patterned resist having a thickness less than 850 nanometers is formed on the multi-layer antireflective layer and the substrate is fabricated using the patterned resist as a mask.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: June 2, 1998
    Assignees: Kabushiki Kaisha Toshiba, International Business Machines Corp.
    Inventors: Tsukasa Azuma, Tokuhisa Ohiwa, Tetsuo Matsuda, David M. Dobuzinsky, Katsuya Okumura
  • Patent number: 5716468
    Abstract: A rotor forging composed of Cr--Mo--V type alloy based on iron is normalizing-treated at a temperature of from 1000 to 1150.degree. C., the temperature is maintained at 650.degree.-750.degree. C. on the way of cooling the temperature from the normalizing-treating temperature to pearlite transform the microstructure of the rotor forging, the portions of the rotor forging corresponding to a high pressure or middle pressure portion are quenched at 940.degree.-1020.degree. C. and the portion corresponding to the low pressure portion is quenched at 850.degree.-940.degree. C. after the heat treatment is carried out at 920.degree.-950.degree. C. once or more times, and the rotor forging is subjected to tempering at 550.degree.-700.degree. C. once or more times. A high creep strength at the high and middle pressure portions can be obtained and, at the same time, the toughness at the low pressure portion is drastically enhanced.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: February 10, 1998
    Assignees: The Japan Steel Works, Ltd., Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko Tanaka, Yasumi Ikeda, Tsukasa Azuma, Masayuki Yamada, Yoichi Tsuda
  • Patent number: 5712698
    Abstract: New types of apertures to vary the size and shape of the aperture area without the need to change the whole aperture plate in off axis lithography. The off axis illumination apertures allow the size and shape of apertures to be changed without having to change the aperture plates for each step in the lithographic process. The aperture plate is fitted with simple shutter mechanisms that allow the ready adjustment of the aperture openings.
    Type: Grant
    Filed: March 4, 1996
    Date of Patent: January 27, 1998
    Assignees: Siemens Aktiengesellschaft, Kabushiki Kaisha Toshiba
    Inventors: Bernhard Poschenrieder, Takashi Sato, Tsukasa Azuma
  • Patent number: 5560788
    Abstract: A heat resisting steels comprising, on percentage by weight basis, 0.05 to 0.2% of C, not more than 1.0% of Ni, 9 to 13% of Cr, 0.05 to 1% of Mo, 0.05 to 0.3% of V, 1 to 3% of W, 1 to 5% of Co, 0.01 to 0.1% of N, at least one member selected from 0.01 to 0.15% of Nb, 0.01 to 0.15% of Ta, 0.003 to 0.03% of a rare earth element, 0.003 to 0.03% of Ca and 0.003 to 0.03% of B, and the remainder of Fe and unavoidable impurities have enhanced high temperature characteristics and are suitable for use in parts of turbine such as turbine rotors, turbine blades, turbine disks and bolts.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: October 1, 1996
    Assignees: The Japan Steel Works, Ltd., Toshiba Corporation
    Inventors: Masayuki Yamada, Yoichi Tsuda, Ryuichi Ishii, Eiji Maeda, Tsukasa Azuma
  • Patent number: 5524019
    Abstract: An object of the invention is to provide an ingot having improvement of and a prevention of occurrence of segregation when electroslag remelting method is used for producing a large size ingot and a super alloy which is sensitive to segregation. According to the present invention, the electrode for electroslag remelting method has a hole formed along an axial direction in the core of an electrode. Therefore, the molten pool is made shallow so that flat and segregation is prevented from occurring. Consequently, an ESR ingot of good quality is accomplished with an excellent surface and is free from segregation. Moreover, an electrode melting rate is increasing and efficiency is improved.
    Type: Grant
    Filed: June 9, 1993
    Date of Patent: June 4, 1996
    Assignee: The Japan Steel Works, Ltd.
    Inventors: Tomoo Takenouchi, Yoshiaki Ichinomiya, Junji Ishizaka, Junji Itagaki, Shuzo Ohhashi, Tsukasa Azuma, Yasuhiko Tanaka
  • Patent number: 5487082
    Abstract: A process for producing a turbine rotor using an ingot in which segregation is prevented effectively when ESR is used to produce a large-sized ingot. A hole is formed along an axial direction in the core of an electrode. The molten pool is made shallow and flat and segregation is prevented from occurring. Consequently, an ESR ingot of good quality offering an excellent surface is obtainable as it is free from segregation. Moreover, an electrode melting rate is increased and efficiency is improved so that a high quality turbine can be manufactured from the ingot.
    Type: Grant
    Filed: May 17, 1994
    Date of Patent: January 23, 1996
    Assignee: The Japan Steel Works, Ltd.
    Inventors: Tomoo Takenouchi, Yoshiaki Ichinomiya, Junji Ishizaka, Junji Itagaki, Shuzo Ohhashi, Tsukasa Azuma, Yasuhiko Tanaka
  • Patent number: 5444732
    Abstract: An object of the present invention is to provide an ingot wherein occurrence is prevented when an electroslag remelting method is used for producing a large ingot and which a super alloy is sensitive to segragation. According to the present invention, the electrode for electroslag remelting method has a hole formed along an axial direction in the core of an electrode. Therefore, the molten pool is made shallow so that flat and segregation is prevented from occurring. Consequently, an ESR ingot of good quality is accomplished with an excellent surface and is free from segregation. Moreover, an electrode melting rate is increasing and efficiency is improved.
    Type: Grant
    Filed: May 17, 1994
    Date of Patent: August 22, 1995
    Assignee: The Japan Steel Works
    Inventors: Tomoo Takenouchi, Yoshiaki Ichinomiya, Junji Ishizaka, Junji Itagaki, Shuzo Ohhashi, Tsukasa Azuma, Yasuhiko Tanaka