Patents by Inventor Tsunenobu Kimoto
Tsunenobu Kimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071764Abstract: A SiC semiconductor device manufacturing method includes a step of etching a surface of a SiC substrate 1 with H2 gas under Si-excess atmosphere within a temperature range of 1000° C. to 1350° C., a step of depositing, by a CVD method, a SiO2 film 2 on the SiC substrate 1 at such a temperature that the SiC substrate 1 is not oxidized, and a step of thermally treating the SiC substrate 1, on which the SiO2 film 2 is deposited, in NO gas atmosphere within a temperature range of 1150° C. to 1350° C.Type: ApplicationFiled: October 22, 2021Publication date: February 29, 2024Applicant: KYOTO UNIVERSITYInventors: Tsunenobu KIMOTO, Keita TACHIKI
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Publication number: 20230307503Abstract: A SiC semiconductor device manufacturing method includes a step of etching a surface of a SiC substrate 1 with H2 gas at a temperature of 1200° C. or more, a step of forming a SiO2 film 3, 4 on the SiC substrate under conditions where the SiC substrate is not oxidized, and a step of thermally treating the SiC substrate formed with the SiO2 film in N2 gas atmosphere at a temperature of 1350° C. or more.Type: ApplicationFiled: May 27, 2021Publication date: September 28, 2023Applicant: KYOTO UNIVERSITYInventors: Tsunenobu KIMOTO, Takuma KOBAYASHI, Keita TACHIKI
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Patent number: 11725301Abstract: The method for manufacturing a crystal for a synthetic gem includes the step of preparing a SiC single crystal including an n-type impurity, and the step of irradiating the SiC single crystal with an electron beam to generate a carbon vacancy in the SiC single crystal. Irradiation energy and dose in electron beam irradiation are set such that the density of the carbon vacancy is higher than the density of the n-type impurity.Type: GrantFiled: November 26, 2021Date of Patent: August 15, 2023Assignee: BRILLAR CO., LTD.Inventors: Iso Ohara, Tsunenobu Kimoto
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Publication number: 20230019556Abstract: A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×1022 cm-3 or more, a SiO2 layer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiO2 layer and in which a carbon density gradually decreases toward the non-connection surface of the SiO2 layer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiO2 layer and that has a carbon density of 1.0×1019 cm-3 or less.Type: ApplicationFiled: September 28, 2022Publication date: January 19, 2023Inventors: Tsunenobu KIMOTO, Takuma KOBAYASHI, Yuki NAKANO, Masatoshi AKETA
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Patent number: 11502172Abstract: A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×1022 cm?3 or more, a SiO2 layer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiO2 layer and in which a carbon density gradually decreases toward the non-connection surface of the SiO2 layer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiO2 layer and that has a carbon density of 1.0×1019 cm?3 or less.Type: GrantFiled: January 10, 2019Date of Patent: November 15, 2022Assignee: ROHM CO., LTD.Inventors: Tsunenobu Kimoto, Takuma Kobayashi, Yuki Nakano, Masatoshi Aketa
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Publication number: 20220251729Abstract: The method for manufacturing a crystal for a synthetic gem includes the step of preparing a SiC single crystal including an n-type impurity, and the step of irradiating the SiC single crystal with an electron beam to generate a carbon vacancy in the SiC single crystal. Irradiation energy and dose in electron beam irradiation are set such that the density of the carbon vacancy is higher than the density of the n-type impurity.Type: ApplicationFiled: November 26, 2021Publication date: August 11, 2022Applicant: BRILLAR CO., LTD.Inventors: Iso OHARA, Tsunenobu KIMOTO
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Publication number: 20200403069Abstract: A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×1022 cm?3 or more, a SiO2 layer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiO2 layer and in which a carbon density gradually decreases toward the non-connection surface of the SiO2 layer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiO2 layer and that has a carbon density of 1.0×1019 cm?3 or less.Type: ApplicationFiled: January 10, 2019Publication date: December 24, 2020Inventors: Tsunenobu KIMOTO, Takuma KOBAYASHI, Yuki NAKANO, Masatoshi AKETA
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Patent number: 9508802Abstract: A process for producing a semiconductor device includes: forming an SiC epitaxial layer on an SiC substrate; implanting the epitaxial layer with ions; forming a gettering layer having a higher defect density than a defect density of the SiC substrate; and carrying out a heat treatment on the epitaxial layer. The semiconductor device includes an SiC substrate, an SiC epitaxial layer formed on the SiC substrate, and a gettering layer having a higher defect density than a defect density of the SiC substrate.Type: GrantFiled: May 4, 2012Date of Patent: November 29, 2016Assignees: Toyota Jidosha Kabushiki Kaisha, Kyoto UniversityInventors: Katsunori Danno, Hiroaki Saitoh, Akinori Seki, Tsunenobu Kimoto
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Patent number: 9190482Abstract: A method of production of an SiC semiconductor device, which can form an ohmic electrode while preventing electrode metal from diffusing in the SiC single crystal substrate, includes a step of forming an ohmic electrode on an SiC substrate, characterized by forming a gettering layer with a defect density higher than the SiC substrate on that substrate to be parallel with the substrate surface, then forming the ohmic electrode the gettering layer outward from the substrate.Type: GrantFiled: August 30, 2012Date of Patent: November 17, 2015Assignees: Toyota Jidosha Kabushiki Kaisha, Kyoto UniversityInventors: Katsunori Danno, Tsunenobu Kimoto
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Publication number: 20150064882Abstract: A process for producing a semiconductor device includes: forming an SiC epitaxial layer on an SiC substrate; implanting the epitaxial layer with ions; forming a gettering layer having a higher defect density than a defect density of the SiC substrate; and carrying out a heat treatment on the epitaxial layer. The semiconductor device includes an SiC substrate, an SiC epitaxial layer formed on the SiC substrate, and a gettering layer having a higher defect density than a defect density of the SiC substrate.Type: ApplicationFiled: May 4, 2012Publication date: March 5, 2015Inventors: Katsunori Danno, Hiroaki Saitoh, Akinori Seki, Tsunenobu Kimoto
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Patent number: 8696814Abstract: A disclosed film deposition apparatus includes a process chamber inside which a reduced pressure space is maintained; a gas supplying portion that supplies a film deposition gas to the process chamber; a substrate holding portion that is made of a material including carbon as a primary constituent and holds a substrate in the process chamber; a coil that is arranged outside the process chamber and inductively heats the substrate holding portion; and a thermal insulation member that covers the substrate holding portion and is arranged to be separated from the process chamber, wherein the reduced pressure space is separated into a film deposition gas supplying space to which the film deposition gas is supplied and a thermal insulation space defined between the substrate holding portion and the process chamber, and wherein a cooling medium is supplied to the thermal insulation space.Type: GrantFiled: November 29, 2007Date of Patent: April 15, 2014Assignees: Tokyo Electron Limited, Rohm Co., Ltd.Inventors: Eisuke Morisaki, Hirokatsu Kobayashi, Jun Yoshikawa, Ikuo Sawada, Tsunenobu Kimoto, Noriaki Kawamoto, Masatoshi Aketa
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Patent number: 8399888Abstract: A p-type SiC semiconductor includes a SiC crystal that contains Al and Ti as impurities, wherein the atom number concentration of Ti is equal to or less than the atom number concentration of Al. It is preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)?5×1018/cm3; and 0.01%?(Concentration of Ti)/(Concentration of Al)?20%. It is more preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)?5×1018/cm3; and 1×1017/cm3?(Concentration of Ti)?1×1018/cm3.Type: GrantFiled: November 19, 2009Date of Patent: March 19, 2013Assignee: Toyota Jidosha Kabushiki KaishaInventors: Hiroaki Saitoh, Akinori Seki, Tsunenobu Kimoto
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Publication number: 20130059429Abstract: A method of production of an SiC semiconductor device, which can form an ohmic electrode while preventing electrode metal from diffusing in the SiC single crystal substrate, includes a step of forming an ohmic electrode on an SiC substrate, characterized by forming a gettering layer with a defect density higher than the SiC substrate on that substrate to be parallel with the substrate surface, then forming the ohmic electrode the gettering layer outward from the substrate.Type: ApplicationFiled: August 30, 2012Publication date: March 7, 2013Inventors: Katsunori Danno, Tsunenobu Kimoto
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Publication number: 20110210341Abstract: A p-type SiC semiconductor includes a SiC crystal that contains Al and Ti as impurities, wherein the atom number concentration of Ti is equal to or less than the atom number concentration of Al. It is preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)?5×1018/cm3; and 0.01%?(Concentration of Ti)/(Concentration of Al)?20%. It is more preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)?5×1018/cm3; and 1×1017/cm3?(Concentration of Ti)?1×1018/cm3.Type: ApplicationFiled: November 19, 2009Publication date: September 1, 2011Inventors: Hiroaki Saitoh, Akinori Seki, Tsunenobu Kimoto
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Patent number: 7837789Abstract: A method of epitaxial growth of a 4H—SiC single crystal enabling growth of an SiC single crystal with low defects and low impurities able to be used for a semiconductor material at a practical growth rate, comprising growing a 4H—SiC single crystal on a 4H—SiC single crystal substrate by epitaxial growth while inclining an epitaxial growth plane of the substrate from a (0001) plane of the 4H—SiC single crystal by an off-angle of at least 12 degrees and less than 30 degrees in a <11-20> axial direction, and a 4H—SiC single crystal obtained by the same.Type: GrantFiled: May 13, 2005Date of Patent: November 23, 2010Assignees: Toyota Jidosha Kabushiki Kaisha, Sumitomo Electric Industries, Ltd.Inventors: Tsunenobu Kimoto, Hiromu Shiomi, Hiroaki Saitoh
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Publication number: 20100092666Abstract: A disclosed film deposition apparatus includes a process chamber inside which a reduced pressure space is maintained; a gas supplying portion that supplies a film deposition gas to the process chamber; a substrate holding portion that is made of a material including carbon as a primary constituent and holds a substrate in the process chamber; a coil that is arranged outside the process chamber and inductively heats the substrate holding portion; and a thermal insulation member that covers the substrate holding portion and is arranged to be separated from the process chamber, wherein the reduced pressure space is separated into a film deposition gas supplying space to which the film deposition gas is supplied and a thermal insulation space defined between the substrate holding portion and the process chamber, and wherein a cooling medium is supplied to the thermal insulation space.Type: ApplicationFiled: November 29, 2007Publication date: April 15, 2010Applicant: Tokyo Electron LimitedInventors: Eisuke Morisaki, Hirokatsu Kobayashi, Jun Yoshikawa, Ikuo Sawada, Tsunenobu Kimoto, Noriaki Kawamoto, Masatoshi Aketa
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Publication number: 20100072485Abstract: One atomic layer of Si atoms 3 is grown on an Si-terminated SiC surface 1a having an Si polar face, and one atomic layer of C atoms 5 is further grown thereon. Then, Si and C are supplied to form an SiC layer. The surface of the SiC layer thus grown is a C polar face opposite to the Si polar face. That is, according to the above-described step, it is possible to grow an SiC polarity-reversed layer 1x having a C polarity on an SiC layer 1 having an Si polarity, with one atomic layer of an Si intermediate layer b interposed therebetween. Consequently, it is possible to provide a technique to reverse the polarity of SiC on the surface.Type: ApplicationFiled: March 25, 2008Publication date: March 25, 2010Inventors: Jun Suda, Tsunenobu Kimoto
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Patent number: 7671388Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.Type: GrantFiled: September 1, 2009Date of Patent: March 2, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
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Patent number: 7671387Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.Type: GrantFiled: July 24, 2008Date of Patent: March 2, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
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Patent number: RE43840Abstract: A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is <11-20>. A trench is formed on the SiC to have a stripe structure extending toward a <11-20> direction. An SiC epitaxial layer is formed on an inside surface of the trench.Type: GrantFiled: October 21, 2010Date of Patent: December 4, 2012Assignee: DENSO CORPORATIONInventors: Mitsuhiro Kataoka, Yuuichi Takeuchi, Masami Naito, Rajesh Kumar, Hiroyuki Matsunami, Tsunenobu Kimoto