Patents by Inventor Tsunenobu Kimoto

Tsunenobu Kimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071764
    Abstract: A SiC semiconductor device manufacturing method includes a step of etching a surface of a SiC substrate 1 with H2 gas under Si-excess atmosphere within a temperature range of 1000° C. to 1350° C., a step of depositing, by a CVD method, a SiO2 film 2 on the SiC substrate 1 at such a temperature that the SiC substrate 1 is not oxidized, and a step of thermally treating the SiC substrate 1, on which the SiO2 film 2 is deposited, in NO gas atmosphere within a temperature range of 1150° C. to 1350° C.
    Type: Application
    Filed: October 22, 2021
    Publication date: February 29, 2024
    Applicant: KYOTO UNIVERSITY
    Inventors: Tsunenobu KIMOTO, Keita TACHIKI
  • Publication number: 20230307503
    Abstract: A SiC semiconductor device manufacturing method includes a step of etching a surface of a SiC substrate 1 with H2 gas at a temperature of 1200° C. or more, a step of forming a SiO2 film 3, 4 on the SiC substrate under conditions where the SiC substrate is not oxidized, and a step of thermally treating the SiC substrate formed with the SiO2 film in N2 gas atmosphere at a temperature of 1350° C. or more.
    Type: Application
    Filed: May 27, 2021
    Publication date: September 28, 2023
    Applicant: KYOTO UNIVERSITY
    Inventors: Tsunenobu KIMOTO, Takuma KOBAYASHI, Keita TACHIKI
  • Patent number: 11725301
    Abstract: The method for manufacturing a crystal for a synthetic gem includes the step of preparing a SiC single crystal including an n-type impurity, and the step of irradiating the SiC single crystal with an electron beam to generate a carbon vacancy in the SiC single crystal. Irradiation energy and dose in electron beam irradiation are set such that the density of the carbon vacancy is higher than the density of the n-type impurity.
    Type: Grant
    Filed: November 26, 2021
    Date of Patent: August 15, 2023
    Assignee: BRILLAR CO., LTD.
    Inventors: Iso Ohara, Tsunenobu Kimoto
  • Publication number: 20230019556
    Abstract: A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×1022 cm-3 or more, a SiO2 layer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiO2 layer and in which a carbon density gradually decreases toward the non-connection surface of the SiO2 layer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiO2 layer and that has a carbon density of 1.0×1019 cm-3 or less.
    Type: Application
    Filed: September 28, 2022
    Publication date: January 19, 2023
    Inventors: Tsunenobu KIMOTO, Takuma KOBAYASHI, Yuki NAKANO, Masatoshi AKETA
  • Patent number: 11502172
    Abstract: A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×1022 cm?3 or more, a SiO2 layer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiO2 layer and in which a carbon density gradually decreases toward the non-connection surface of the SiO2 layer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiO2 layer and that has a carbon density of 1.0×1019 cm?3 or less.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: November 15, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Tsunenobu Kimoto, Takuma Kobayashi, Yuki Nakano, Masatoshi Aketa
  • Publication number: 20220251729
    Abstract: The method for manufacturing a crystal for a synthetic gem includes the step of preparing a SiC single crystal including an n-type impurity, and the step of irradiating the SiC single crystal with an electron beam to generate a carbon vacancy in the SiC single crystal. Irradiation energy and dose in electron beam irradiation are set such that the density of the carbon vacancy is higher than the density of the n-type impurity.
    Type: Application
    Filed: November 26, 2021
    Publication date: August 11, 2022
    Applicant: BRILLAR CO., LTD.
    Inventors: Iso OHARA, Tsunenobu KIMOTO
  • Publication number: 20200403069
    Abstract: A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×1022 cm?3 or more, a SiO2 layer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiO2 layer and in which a carbon density gradually decreases toward the non-connection surface of the SiO2 layer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiO2 layer and that has a carbon density of 1.0×1019 cm?3 or less.
    Type: Application
    Filed: January 10, 2019
    Publication date: December 24, 2020
    Inventors: Tsunenobu KIMOTO, Takuma KOBAYASHI, Yuki NAKANO, Masatoshi AKETA
  • Patent number: 9508802
    Abstract: A process for producing a semiconductor device includes: forming an SiC epitaxial layer on an SiC substrate; implanting the epitaxial layer with ions; forming a gettering layer having a higher defect density than a defect density of the SiC substrate; and carrying out a heat treatment on the epitaxial layer. The semiconductor device includes an SiC substrate, an SiC epitaxial layer formed on the SiC substrate, and a gettering layer having a higher defect density than a defect density of the SiC substrate.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: November 29, 2016
    Assignees: Toyota Jidosha Kabushiki Kaisha, Kyoto University
    Inventors: Katsunori Danno, Hiroaki Saitoh, Akinori Seki, Tsunenobu Kimoto
  • Patent number: 9190482
    Abstract: A method of production of an SiC semiconductor device, which can form an ohmic electrode while preventing electrode metal from diffusing in the SiC single crystal substrate, includes a step of forming an ohmic electrode on an SiC substrate, characterized by forming a gettering layer with a defect density higher than the SiC substrate on that substrate to be parallel with the substrate surface, then forming the ohmic electrode the gettering layer outward from the substrate.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: November 17, 2015
    Assignees: Toyota Jidosha Kabushiki Kaisha, Kyoto University
    Inventors: Katsunori Danno, Tsunenobu Kimoto
  • Publication number: 20150064882
    Abstract: A process for producing a semiconductor device includes: forming an SiC epitaxial layer on an SiC substrate; implanting the epitaxial layer with ions; forming a gettering layer having a higher defect density than a defect density of the SiC substrate; and carrying out a heat treatment on the epitaxial layer. The semiconductor device includes an SiC substrate, an SiC epitaxial layer formed on the SiC substrate, and a gettering layer having a higher defect density than a defect density of the SiC substrate.
    Type: Application
    Filed: May 4, 2012
    Publication date: March 5, 2015
    Inventors: Katsunori Danno, Hiroaki Saitoh, Akinori Seki, Tsunenobu Kimoto
  • Patent number: 8696814
    Abstract: A disclosed film deposition apparatus includes a process chamber inside which a reduced pressure space is maintained; a gas supplying portion that supplies a film deposition gas to the process chamber; a substrate holding portion that is made of a material including carbon as a primary constituent and holds a substrate in the process chamber; a coil that is arranged outside the process chamber and inductively heats the substrate holding portion; and a thermal insulation member that covers the substrate holding portion and is arranged to be separated from the process chamber, wherein the reduced pressure space is separated into a film deposition gas supplying space to which the film deposition gas is supplied and a thermal insulation space defined between the substrate holding portion and the process chamber, and wherein a cooling medium is supplied to the thermal insulation space.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: April 15, 2014
    Assignees: Tokyo Electron Limited, Rohm Co., Ltd.
    Inventors: Eisuke Morisaki, Hirokatsu Kobayashi, Jun Yoshikawa, Ikuo Sawada, Tsunenobu Kimoto, Noriaki Kawamoto, Masatoshi Aketa
  • Patent number: 8399888
    Abstract: A p-type SiC semiconductor includes a SiC crystal that contains Al and Ti as impurities, wherein the atom number concentration of Ti is equal to or less than the atom number concentration of Al. It is preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)?5×1018/cm3; and 0.01%?(Concentration of Ti)/(Concentration of Al)?20%. It is more preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)?5×1018/cm3; and 1×1017/cm3?(Concentration of Ti)?1×1018/cm3.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: March 19, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hiroaki Saitoh, Akinori Seki, Tsunenobu Kimoto
  • Publication number: 20130059429
    Abstract: A method of production of an SiC semiconductor device, which can form an ohmic electrode while preventing electrode metal from diffusing in the SiC single crystal substrate, includes a step of forming an ohmic electrode on an SiC substrate, characterized by forming a gettering layer with a defect density higher than the SiC substrate on that substrate to be parallel with the substrate surface, then forming the ohmic electrode the gettering layer outward from the substrate.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 7, 2013
    Inventors: Katsunori Danno, Tsunenobu Kimoto
  • Publication number: 20110210341
    Abstract: A p-type SiC semiconductor includes a SiC crystal that contains Al and Ti as impurities, wherein the atom number concentration of Ti is equal to or less than the atom number concentration of Al. It is preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)?5×1018/cm3; and 0.01%?(Concentration of Ti)/(Concentration of Al)?20%. It is more preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)?5×1018/cm3; and 1×1017/cm3?(Concentration of Ti)?1×1018/cm3.
    Type: Application
    Filed: November 19, 2009
    Publication date: September 1, 2011
    Inventors: Hiroaki Saitoh, Akinori Seki, Tsunenobu Kimoto
  • Patent number: 7837789
    Abstract: A method of epitaxial growth of a 4H—SiC single crystal enabling growth of an SiC single crystal with low defects and low impurities able to be used for a semiconductor material at a practical growth rate, comprising growing a 4H—SiC single crystal on a 4H—SiC single crystal substrate by epitaxial growth while inclining an epitaxial growth plane of the substrate from a (0001) plane of the 4H—SiC single crystal by an off-angle of at least 12 degrees and less than 30 degrees in a <11-20> axial direction, and a 4H—SiC single crystal obtained by the same.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: November 23, 2010
    Assignees: Toyota Jidosha Kabushiki Kaisha, Sumitomo Electric Industries, Ltd.
    Inventors: Tsunenobu Kimoto, Hiromu Shiomi, Hiroaki Saitoh
  • Publication number: 20100092666
    Abstract: A disclosed film deposition apparatus includes a process chamber inside which a reduced pressure space is maintained; a gas supplying portion that supplies a film deposition gas to the process chamber; a substrate holding portion that is made of a material including carbon as a primary constituent and holds a substrate in the process chamber; a coil that is arranged outside the process chamber and inductively heats the substrate holding portion; and a thermal insulation member that covers the substrate holding portion and is arranged to be separated from the process chamber, wherein the reduced pressure space is separated into a film deposition gas supplying space to which the film deposition gas is supplied and a thermal insulation space defined between the substrate holding portion and the process chamber, and wherein a cooling medium is supplied to the thermal insulation space.
    Type: Application
    Filed: November 29, 2007
    Publication date: April 15, 2010
    Applicant: Tokyo Electron Limited
    Inventors: Eisuke Morisaki, Hirokatsu Kobayashi, Jun Yoshikawa, Ikuo Sawada, Tsunenobu Kimoto, Noriaki Kawamoto, Masatoshi Aketa
  • Publication number: 20100072485
    Abstract: One atomic layer of Si atoms 3 is grown on an Si-terminated SiC surface 1a having an Si polar face, and one atomic layer of C atoms 5 is further grown thereon. Then, Si and C are supplied to form an SiC layer. The surface of the SiC layer thus grown is a C polar face opposite to the Si polar face. That is, according to the above-described step, it is possible to grow an SiC polarity-reversed layer 1x having a C polarity on an SiC layer 1 having an Si polarity, with one atomic layer of an Si intermediate layer b interposed therebetween. Consequently, it is possible to provide a technique to reverse the polarity of SiC on the surface.
    Type: Application
    Filed: March 25, 2008
    Publication date: March 25, 2010
    Inventors: Jun Suda, Tsunenobu Kimoto
  • Patent number: 7671388
    Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: March 2, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
  • Patent number: 7671387
    Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: March 2, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
  • Patent number: RE43840
    Abstract: A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is <11-20>. A trench is formed on the SiC to have a stripe structure extending toward a <11-20> direction. An SiC epitaxial layer is formed on an inside surface of the trench.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: December 4, 2012
    Assignee: DENSO CORPORATION
    Inventors: Mitsuhiro Kataoka, Yuuichi Takeuchi, Masami Naito, Rajesh Kumar, Hiroyuki Matsunami, Tsunenobu Kimoto