Abstract: A SiC wafer comprises a 4H polytype SiC substrate 2 in which the crystal plane orientation is substantially {03-38}, and a buffer layer 4 composed of SiC formed over this SiC substrate 2. The {03-38} plane forms an angle of approximately 35° with respect to the <0001> axial direction in which micropipes and so forth extend, so micropipes and so forth are eliminated at the crystal sides, and do not go through to an active layer 6 on the buffer layer 4. Lattice mismatching between the SiC substrate 2 and the active layer 6 is suppressed by the buffer layer 4. Furthermore, anisotropy in the electron mobility is low because a 4H polytype is used. Therefore, it is possible to obtain a SiC wafer and a SiC semiconductor device with which there is little anisotropy in the electron mobility, and strain caused by lattice mismatching can be lessened, as well as a method for manufacturing these.

Abstract: A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is <11-20>. A trench is formed on the SiC to have a stripe structure extending toward a <11-20> direction. An SiC epitaxial layer is formed on an inside surface of the trench.

Abstract: A method of growing a 4H-poly type SiC single crystal 40, characterized in that the 4H-poly type SiC single crystal 40 is grown on a seed crystal 30 comprised of an SiC single crystal where a {03-38} plane 30u or a plane which is inclined at off angle &agr;, within about 10°, with respect to the {03-38} plane, is exposed.

Abstract: A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.

Abstract: A semiconductor heterojunction structure comprising a p-type diamond layer and an n-type cubic boron nitride layer on a surface of said p-type diamond layer. Such heterojunction structure is useful for a semiconductor device such as a diode, a transistor, a laser and a rectifier, particularly an element which emits light from blue light to ultraviolet light.

Abstract: A heating process for producing a high quality diamond or c-BN film on a diamond or c-BN substrate comprising placing a diamond or c-BN substrate in vacuum, elevating the temperature and treating its surface with a chlorine containing gas, a fluorine containing gas, a nitrogen containing plasma or a hydrogen containing plasma. The treatment gas is then removed and feed gases are introduced which are suitable for growing a thin diamond or c-BN film on the surface substrate under chemical vapor deposition conditions.

Abstract: A semiconductor heterojunction structure comprising a p-type diamond layer and an n-type cubic boron nitride layer on a surface of said p-type diamond layer. Such heterojunction structure is useful for a semiconductor device such as a diode, a transistor, a laser and a rectifier, particularly an element which emits light from blue light to ultraviolet light.