Patents by Inventor Tsunenobu Kimoto
Tsunenobu Kimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7671387Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.Type: GrantFiled: July 24, 2008Date of Patent: March 2, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
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Publication number: 20090315082Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.Type: ApplicationFiled: September 1, 2009Publication date: December 24, 2009Applicant: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
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Publication number: 20090261362Abstract: 4H—InGaAlN alloy based optoelectronic and electronic devices on non-polar face are formed on 4H—AlN or 4H—AlGaN on (11-20) a-face 4H—SiC substrates. Typically, non polar 4H—AlN is grown on 4H—SiC (11-20) by molecular beam epitaxy (MBE). Subsequently, III-V nitride device layers are grown by metal organic chemical vapor deposition (MOCVD) with 4H-polytype for all of the layers. The non-polar device does not contain any built-in electric field due to the spontaneous and piezoelectric polarization. The optoelectronic devices on the non-polar face exhibits higher emission efficiency with shorter emission wavelength because the electrons and holes are not spatially separated in the quantum well. Vertical device configuration for lasers and light emitting diodes (LEDs) using conductive 4H—AlGaN interlayer on conductive 4H—SiC substrates makes the chip size and series resistance smaller. The elimination of such electric field also improves the performance of high speed and high power transistors.Type: ApplicationFiled: July 1, 2009Publication date: October 22, 2009Applicant: PANASONIC CORPORATIONInventors: Tetsuzo UEDA, Tsunenobu Kimoto, Hiroyuki Matsunami, Jun Suda, Norio Onojima
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Patent number: 7528426Abstract: A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.Type: GrantFiled: January 20, 2006Date of Patent: May 5, 2009Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Harada, Kenichi Hirotsu, Hiroyuki Matsunami, Tsunenobu Kimoto
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Publication number: 20090072243Abstract: In the present invention, a technology for causing arbitrary polarity, crystal face and crystal orientation to exist mixedly in a plane on the surface of a SiC substrate, and for forming a SiC layer or a group III-nitride or group II-oxide layer on the surface, is provided. A first SiC substrate 41 having (0001) face and a second SiC substrate 44 having (000-1) face are prepared. An oxide film 43 is formed on the surfaces of the SiC substrates 41 and 44 by subjecting them to an oxidation treatment, and then the two SiC substrates are fusion-bonded so that the rear surface of the second SiC substrate and the surface of the first SiC substrate are brought into contact with each other. Subsequently, a part corresponding to the second SiC substrate 44 is made thin (44a). Subsequently, a thin layer 44a of the second SiC substrate is removed in accordance with required periodic reversal to be processed in stripes by using a lithography technology and reactive ion etching technology.Type: ApplicationFiled: April 5, 2006Publication date: March 19, 2009Inventors: Jun Suda, Tsunenobu Kimoto
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Publication number: 20080277696Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.Type: ApplicationFiled: July 24, 2008Publication date: November 13, 2008Applicant: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
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Patent number: 7420232Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.Type: GrantFiled: April 11, 2006Date of Patent: September 2, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
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Patent number: 7321142Abstract: On an SiC single crystal substrate, an electric field relaxation layer and a p? type buffer layer are formed. The electric field relaxation layer is formed between the p? type buffer layer and the SiC single crystal substrate to contact SiC single crystal substrate. On the p? type buffer layer, an n type semiconductor layer is formed. On the n type semiconductor layer, a p type semiconductor layer is formed. In the p type semiconductor layer, an n+ type source region layer and an n+ type drain region layer are formed separated by a prescribed distance from each other. At a part of the region of p type semiconductor layer between the n+ type source region layer and the n+ type drain region layer, a p+ type gate region layer is formed.Type: GrantFiled: May 21, 2004Date of Patent: January 22, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada, Hiroyuki Matsunami, Tsunenobu Kimoto
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Publication number: 20070221119Abstract: A method of epitaxial growth of a 4H—SiC single crystal enabling growth of an SiC single crystal with low defects and low impurities able to be used for a semiconductor material at a practical growth rate, comprising growing a 4H—SiC single crystal on a 4H—SiC single crystal substrate by epitaxial growth while inclining an epitaxial growth plane of the substrate from a (0001) plane of the 4H—SiC single crystal by an off-angle of at least 12 degrees and less than 30 degrees in a <11-20> axial direction, and a 4H—SiC single crystal obtained by the same.Type: ApplicationFiled: May 13, 2005Publication date: September 27, 2007Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, SIXON LTDInventors: Tsunenobu Kimoto, Hiromu Shiomi, Hiroaki Saitoh
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Patent number: 7241694Abstract: A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600° C.Type: GrantFiled: April 14, 2005Date of Patent: July 10, 2007Assignee: DENSO CorporationInventors: Yuuichi Takeuchi, Rajesh Kumar Malhan, Hiroyuki Matsunami, Tsunenobu Kimoto
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Publication number: 20060202238Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.Type: ApplicationFiled: April 11, 2006Publication date: September 14, 2006Applicant: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
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Publication number: 20060118813Abstract: A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.Type: ApplicationFiled: January 20, 2006Publication date: June 8, 2006Applicant: Sumitomo Electric Industries, Ltd.Inventors: Shin Harada, Kenichi Hirotsu, Hiroyuki Matsunami, Tsunenobu Kimoto
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Publication number: 20060113574Abstract: On an SiC single crystal substrate, an electric field relaxation layer and a p? type buffer layer are formed. The electric field relaxation layer is formed between the p? type buffer layer and the SiC single crystal substrate to contact SiC single crystal substrate. On the p? type buffer layer, an n type semiconductor layer is formed. On the n type semiconductor layer, a p type semiconductor layer is formed. In the p type semiconductor layer, an n+ type source region layer and an n+ type drain region layer are formed separated by a prescribed distance from each other. At a part of the region of p type semiconductor layer between the n+ type source region layer and the n+ type drain region layer, a p+ type gate region layer is formed.Type: ApplicationFiled: May 21, 2004Publication date: June 1, 2006Inventors: Kazuhiro Fujikawa, Shin Harada, Hiroyuki Matsunami, Tsunenobu Kimoto
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Patent number: 7049644Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.Type: GrantFiled: December 2, 2002Date of Patent: May 23, 2006Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
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Patent number: 7023033Abstract: A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.Type: GrantFiled: June 11, 2002Date of Patent: April 4, 2006Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Harada, Kenichi Hirotsu, Hiroyuki Matsunami, Tsunenobu Kimoto
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Publication number: 20050233539Abstract: A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600° C.Type: ApplicationFiled: April 14, 2005Publication date: October 20, 2005Inventors: Yuuichi Takeuchi, Rajesh Malhan, Hiroyuki Matsunami, Tsunenobu Kimoto
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Publication number: 20050218414Abstract: 4H-InGaAlN alloy based optoelectronic and electronic devices on non-polar face are formed on 4H-AlN or 4H-AlGaN on (11-20) a-face 4H-SiC substrates. Typically, non polar 4H-AlN is grown on 4H-SiC (11-20) by molecular beam epitaxy (MBE). Subsequently, III-V nitride device layers are grown by metal organic chemical vapor deposition (MOCVD) with 4H-polytype for all of the layers. The non-polar device does not contain any built-in electric field due to the spontaneous and piezoelectric polarization. The optoelectonic devices on the non-polar face exhibits higher emission efficiency with shorter emission wavelength because the electrons and holes are not spatially separated in the quantum well. Vertical device configuration for lasers and light emitting diodes(LEDs) using conductive 4H-AlGaN interlayer on conductive 4H-SiC substrates makes the chip size and series resistance smaller. The elimination of such electric field also improves the performance of high speed and high power transistors.Type: ApplicationFiled: March 30, 2004Publication date: October 6, 2005Inventors: Tetsuzo Ueda, Tsunenobu Kimoto, Hiroyuki Matsunami, Jun Suda, Norio Onojima
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Publication number: 20050093017Abstract: A lateral junction field effect transistor includes a first gate electrode layer (18A) arranged in a third semiconductor layer (13) between source/drain region layers (6, 8), having a lower surface extending on the second semiconductor layer (12), and doped with p-type impurities more heavily than the second semiconductor layer (12), and a second gate electrode layer (18B) arranged in a fifth semiconductor layer (15) between the source/drain region layers (6, 8), having a lower surface extending on a fourth semiconductor layer (14), having substantially the same concentration of p-type impurities as the first gate electrode layer (18A), and having the same potential as the first gate electrode layer (18A). Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.Type: ApplicationFiled: December 2, 2002Publication date: May 5, 2005Inventors: Kazuhiro Fujikawa, Shin Harada, Kenichi Hirotsu, Satoshi Hatsukawa, Takashi Hoshino, Hiroyuki Matsunami, Tsunenobu Kimoto
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Patent number: 6870189Abstract: A junction field effect transistor (JFET) is provided that is capable of a high voltage resistance, high current switching operation, that operates with a low loss, and that has little variation. This JFET is provided with a gate region (2) of a second conductivity type provided on a surface of a semiconductor substrate, a source region (1) of a first conductivity type, a channel region (10) of the first conductivity type that adjoins the source region, a confining region (5) of the second conductivity type that adjoins the gate region and confines the channel region, a drain region (3) of the first conductivity type provided on a reverse face, and a drift region (4) of the first conductivity type that continuously lies in a direction of thickness of the substrate from a channel to a drain.Type: GrantFiled: September 11, 2000Date of Patent: March 22, 2005Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Harada, Kenichi Hirotsu, Hiroyuki Matsunami, Tsunenobu Kimoto
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Patent number: 6853006Abstract: A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is <11-20>. A trench is formed on the SiC to have a stripe structure extending toward a <11-20> direction. An SiC epitaxial layer is formed on an inside surface of the trench.Type: GrantFiled: July 31, 2003Date of Patent: February 8, 2005Assignee: Denso CorporationInventors: Mitsuhiro Kataoka, Yuuichi Takeuchi, Masami Naito, Rajesh Kumar, Hiroyuki Matsunami, Tsunenobu Kimoto