Patents by Inventor Tsung-Hsien Lee
Tsung-Hsien Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240129167Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.Type: ApplicationFiled: September 18, 2023Publication date: April 18, 2024Applicant: MEDIATEK INC.Inventors: Chung-Hsien Tsai, Che-Yu Chiang, Yu-Ting Liu, Tsung-Lin Lee, Chia-Sheng Peng, Ting-Ming Yang
-
Patent number: 11955439Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.Type: GrantFiled: January 17, 2023Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Cheng Wu, Chien-Chia Chiu, Cheng-Hsien Hsieh, Li-Han Hsu, Meng-Tsan Lee, Tsung-Shu Lin
-
Publication number: 20240085753Abstract: An electrochromic composition including: a first oxidizable compound; a reducible compound; an electrolyte; and a solvent, wherein the first oxidizable compound is represented by the following formula: wherein X1, and X2 are independently substituted or unsubstituted aliphatic hydrocarbon groups, or substituted or unsubstituted aromatic hydrocarbon groups, wherein the aromatic hydrocarbon groups include: wherein each Rx is independently hydrogen, a C1-C16 alkyl group, a C1-C16 alkoxy group, a C1-C16 haloalkyl group, or halogen.Type: ApplicationFiled: February 24, 2023Publication date: March 14, 2024Inventors: Hao-Ping HUANG, Tsung-Hsien LIN, Yu-Nan LEE
-
Publication number: 20240063251Abstract: A semiconductor device includes a substrate, a first multilayer capacitor, and a second multilayer capacitor. The first multilayer capacitor includes a first plurality of conductive layers. The semiconductor device further includes a first set of contacts including a first contact electrically connected to a first conductive layer, and a second contact electrically connected to a second conductive layer, wherein the first contact is spaced from the second contact by a first distance. The second multilayer capacitor includes a second plurality of conductive layers. The semiconductor device further includes a second set of contacts including a third contact electrically connected to a third conductive layer, and a fourth contact electrically connected to a fourth conductive layer, wherein the third contact is spaced from the fourth contact by a second distance, and the second distance is different from the first distance.Type: ApplicationFiled: November 2, 2023Publication date: February 22, 2024Inventors: Tao-Cheng LIU, Shih-Chi KUO, Tsai-Hao HUNG, Tsung-Hsien LEE
-
Patent number: 11810945Abstract: A method of making a semiconductor device includes etching a substrate to define a first trench and a second trench. The method further includes depositing a first number M of capacitor layer pairs in the first trench, wherein each of the first number M of capacitor layer pairs includes a first dielectric layer, and a first conductive layer. The method further includes depositing a second number N of capacitor layer pairs in the second trench, wherein the second number N is different from the first number M, and each of the second number N of capacitor layer pairs includes a second dielectric layer, and a second conductive layer. The method further includes planarizing the first number M of capacitor layer pairs and the second number N of capacitor layer pairs to expose the substrate.Type: GrantFiled: December 9, 2020Date of Patent: November 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tao-Cheng Liu, Shih-Chi Kuo, Tsai-Hao Hung, Tsung-Hsien Lee
-
Publication number: 20220310520Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.Type: ApplicationFiled: June 15, 2022Publication date: September 29, 2022Inventors: Fu-Chiang KUO, Tao-Cheng LIU, Shih-Chi KUO, Tsung-Hsien LEE
-
Patent number: 11373952Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.Type: GrantFiled: October 8, 2020Date of Patent: June 28, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Chiang Kuo, Tao-Cheng Liu, Shih-Chi Kuo, Tsung-Hsien Lee
-
Patent number: 11131541Abstract: The present disclosure is directed to a method and system for monitoring a distance between a shutter and a reference point in a processing module. For example, the method includes moving a shutter relative to a substrate support in a wafer processing module and determining a distance between the shutter and a wall of the wafer processing module with a measurement device. In response to the distance being greater than a value, the method further includes transferring a substrate to the substrate support, and in response to the distance being equal to or less than the value, the method includes resetting the shutter.Type: GrantFiled: May 9, 2019Date of Patent: September 28, 2021Inventors: Shih-Yu Liao, Shih-Chi Kuo, Tsai-Hao Hung, Tsung-Hsien Lee
-
Publication number: 20210118978Abstract: A method of making a semiconductor device includes etching a substrate to define a first trench and a second trench. The method further includes depositing a first number M of capacitor layer pairs in the first trench, wherein each of the first number M of capacitor layer pairs includes a first dielectric layer, and a first conductive layer. The method further includes depositing a second number N of capacitor layer pairs in the second trench, wherein the second number N is different from the first number M, and each of the second number N of capacitor layer pairs includes a second dielectric layer, and a second conductive layer. The method further includes planarizing the first number M of capacitor layer pairs and the second number N of capacitor layer pairs to expose the substrate.Type: ApplicationFiled: December 9, 2020Publication date: April 22, 2021Inventors: Tao-Cheng LIU, Shih-Chi KUO, Tsai-Hao HUNG, Tsung-Hsien LEE
-
Publication number: 20210028118Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.Type: ApplicationFiled: October 8, 2020Publication date: January 28, 2021Inventors: Fu-Chiang KUO, Tao-Cheng LIU, Shih-Chi KUO, Tsung-Hsien LEE
-
Patent number: 10868107Abstract: Methods of manufacturing trench capacitors include forming a trench opening in a substrate, depositing a first dielectric layer over a sidewall and a bottom surface of a first trench opening in a substrate, and depositing a first conductive layer over the first dielectric layer. The first dielectric layer and the first conductive layer are then planarized to expose a planarized top surface of the substrate and a planarized top surface of the first conductive layer in the first trench opening. An ILD layer is deposited over the planarized top surface of the substrate and over the planarized surface of the first conductive layer. A first electrical contact is formed through the ILD layer to provide an electrical connection to the first conductive layer within the first trench opening.Type: GrantFiled: June 20, 2017Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tao-Cheng Liu, Shih-Chi Kuo, Tsai-Hao Hung, Tsung-Hsien Lee
-
Patent number: 10804206Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.Type: GrantFiled: February 23, 2018Date of Patent: October 13, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-Chiang Kuo, Tao-Cheng Liu, Shih-Chi Kuo, Tsung-Hsien Lee
-
Publication number: 20200003550Abstract: The present disclosure is directed to a method and system for monitoring a distance between a shutter and a reference point in a processing module. For example, the method includes moving a shutter relative to a substrate support in a wafer processing module and determining a distance between the shutter and a wall of the wafer processing module with a measurement device. In response to the distance being greater than a value, the method further includes transferring a substrate to the substrate support, and in response to the distance being equal to or less than the value, the method includes resetting the shutter.Type: ApplicationFiled: May 9, 2019Publication date: January 2, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Yu LIAO, Shih-Chi Kuo, Tsai-Hao Hung, Tsung-Hsien Lee
-
Patent number: 10508020Abstract: The present disclosure provides a substrate structure for a micro electro mechanical system (MEMS) device. The substrate structure includes a cap and a micro electro mechanical system (MEMS) substrate. The cap has a cavity, and the MEMS substrate is disposed on the cap. The MEMS substrate has a plurality of through holes exposing the cavity, and an aspect ratio of the through hole is greater than 30.Type: GrantFiled: January 20, 2017Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsai-Hao Hung, Shih-Chi Kuo, Tsung-Hsien Lee, Tao-Cheng Liu
-
Patent number: 10424549Abstract: A method of forming a trench structure is provided. The method includes depositing a silicon carbide (SiC) layer on a top metal layer, forming a first passivation layer on the SiC layer, removing a portion of the first passivation layer to form a first opening, forming a second passivation layer on the first passivation layer, the second passivation layer including a first portion in the first opening, and forming a second opening by removing a part of the first portion of the second passivation layer. The forming the second opening exposes the top metal layer.Type: GrantFiled: October 29, 2018Date of Patent: September 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu-Chiang Kuo, Shih-Chi Kuo, Tsung-Hsien Lee, Ying-Hsun Chen
-
Publication number: 20190067215Abstract: A method of forming a trench structure is provided. The method includes depositing a silicon carbide (SiC) layer on a top metal layer, forming a first passivation layer on the SiC layer, removing a portion of the first passivation layer to form a first opening, forming a second passivation layer on the first passivation layer, the second passivation layer including a first portion in the first opening, and forming a second opening by removing a part of the first portion of the second passivation layer. The forming the second opening exposes the top metal layer.Type: ApplicationFiled: October 29, 2018Publication date: February 28, 2019Inventors: Fu-Chiang KUO, Shih-Chi KUO, Tsung-Hsien LEE, Ying-Hsun CHEN
-
Publication number: 20190035736Abstract: A semiconductor device includes: at least one conductive feature disposed on a substrate; at least one dielectric layer overlying the substrate, a trench structure extending through the at least one dielectric layer; and a protection layer overlaying the trench structure.Type: ApplicationFiled: February 23, 2018Publication date: January 31, 2019Inventors: Fu-Chiang KUO, Tao-Cheng Liu, Shih-Chi Kuo, Tsung-Hsien Lee
-
Publication number: 20180366537Abstract: Methods of manufacturing trench capacitors include forming a trench opening in a substrate, depositing a first dielectric layer over a sidewall and a bottom surface of a first trench opening in a substrate, and depositing a first conductive layer over the first dielectric layer. The first dielectric layer and the first conductive layer are then planarized to expose a planarized top surface of the substrate and a planarized top surface of the first conductive layer in the first trench opening. An ILD layer is deposited over the planarized top surface of the substrate and over the planarized surface of the first conductive layer. A first electrical contact is formed through the ILD layer to provide an electrical connection to the first conductive layer within the first trench opening.Type: ApplicationFiled: June 20, 2017Publication date: December 20, 2018Inventors: Tao-Cheng LIU, Shih-Chi KUO, Tsai-Hao HUNG, Tsung-Hsien LEE
-
Patent number: 10146730Abstract: The present disclosure illustrates a device for maintaining serial routing during request transmission and a method thereof. According to an embodiment, the device may select one of serial ports according to a routing rule to transmit a request. When not receiving the response, the corresponding routing data is deleted from the routing rule, and the device transmits the request through all serial ports, and upon receipt of the response, the device adds a piece of corresponding transaction data in the routing rule. As a result, the routing rule may be automatically updated when a new serial device is electrically connected to the gateway or the serial port through which the serial device is electrically connected to the gateway is changed. The technical effect that it is not necessary for the user to particularly set the gateway after installation may be achieved.Type: GrantFiled: July 4, 2017Date of Patent: December 4, 2018Assignee: MOXA INC.Inventors: Tsung-Hsien Lee, Chien-Ho Wang, Chih-Hung Yu
-
Patent number: 10115679Abstract: A trench structure includes a top metal layer, a silicon carbide (SiC) layer on the top metal layer, a first passivation layer overlying the SiC layer, and a second passivation layer overlying the first passivation layer. The trench structure also includes a first sidewall and a second sidewall that, together with the top metal layer, form a trench. At least one of the first sidewall or the second sidewall includes a sidewall of the second passivation layer and a sidewall of the SiC layer.Type: GrantFiled: June 19, 2017Date of Patent: October 30, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fu-Chiang Kuo, Shih-Chi Kuo, Tsung-Hsien Lee, Ying-Hsun Chen