Abstract: The present disclosure illustrates a device for maintaining serial routing during request transmission and a method thereof. According to an embodiment, the device may select one of serial ports according to a routing rule to transmit a request. When not receiving the response, the corresponding routing data is deleted from the routing rule, and the device transmits the request through all serial ports, and upon receipt of the response, the device adds a piece of corresponding transaction data in the routing rule. As a result, the routing rule may be automatically updated when a new serial device is electrically connected to the gateway or the serial port through which the serial device is electrically connected to the gateway is changed. The technical effect that it is not necessary for the user to particularly set the gateway after installation may be achieved.

Abstract: A control device which is in communication with a switch comprises a memory which stores applications. The applications can handle received data streams of the switch. The control device selects first applications from all the applications and transmits the first applications and a command to the switch to install the first applications. The switch itself transmits received data streams to the first applications for processing when external data streams are received.

Abstract: MRAM devices and methods of forming the same are provided. One of the MRAM devices includes a dielectric layer, a resistance variable memory cell and a conductive layer. The dielectric layer is over a substrate and has an opening. The resistance variable memory cell is in the opening and includes a first electrode, a second electrode and a magnetic tunnel junction layer between the first electrode and the second electrode. The conductive layer fills a remaining portion of the opening and is electrically connected to one of the first electrode and the second electrode of the resistance variable memory cell.

Abstract: MRAM devices and methods of forming the same are provided. One of the MRAM devices includes a dielectric layer, a resistance variable memory cell and a conductive layer. The dielectric layer is over a substrate and has an opening. The resistance variable memory cell is in the opening and includes a first electrode, a second electrode and a magnetic tunnel junction layer between the first electrode and the second electrode. The conductive layer fills a remaining portion of the opening and is electrically connected to one of the first electrode and the second electrode of the resistance variable memory cell.

Abstract: A method of generating a set of defect candidates for a wafer is disclosed. The wafer comprises at least one die manufactured according to a mask, and the mask being prepared by combining a plurality of layout areas. The method includes receiving an initial defect information from a wafer scanning device indicating potential defects of a semiconductor wafer and determining a boundary region on the semiconductor wafer. The method further includes creating an exclusion region from the boundary region, the exclusion region having a first set of defects in the potential defects of the semiconductor wafer, and creating filtered defect information by removing the first set of defects from the initial defect information.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack structure and a second gate stack structure on a substrate, and the first gate stack structure includes a first spacer adjacent to the second gate stack structure. The method also includes forming an U-shaped capping layer between the first gate stack structure and the second gate stack structure, and a lateral sidewall of the U-shaped capping layer is in direct contact with the first spacer of the first gate stack structure. A top of the lateral sidewall of the U-shaped capping layer is below a top of the first spacer of the first gate stack structure.

Abstract: A method of forming a deep trench in a semiconductor substrate includes: forming a first mask pattern over the semiconductor substrate, in which the first mask pattern has a first opening exposing a portion of the semiconductor substrate; forming a second mask pattern over the first mask pattern, in which the second mask pattern has a second opening substantially aligned with the first opening to expose the portion of the semiconductor substrate, and the second opening has a width greater than a width of the first opening to further expose a portion of the first mask pattern; and removing the portion of the semiconductor substrate, the portion of first mask pattern and another portion of the semiconductor substrate beneath the portion of the first mask pattern to form the deep trench.

Abstract: The present disclosure provides a substrate structure for a micro electro mechanical system (MEMS) device. The substrate structure includes a cap and a micro electro mechanical system (MEMS) substrate. The cap has a cavity, and the MEMS substrate is disposed on the cap. The MEMS substrate has a plurality of through holes exposing the cavity, and an aspect ratio of the through hole is greater than 30.

Abstract: The present disclosure relates to a method of forming a masking structure having a trench with a high aspect ratio, and an associated structure. In some embodiments, the method is performed by forming a first material over a substrate. The first material is selectively etched and a second material is formed onto the substrate at a position abutting sidewalls of the first material, resulting in a pillar of sacrificial material surrounded by a masking material. The pillar of sacrificial material is removed, resulting in a masking layer having a trench that extends into the masking material. Using the pillar of sacrificial material during formation of the trench allows the trench to have a high aspect ratio. For example, the sacrificial material allows for a plurality of masking layers to be iteratively formed to have laterally aligned openings that collectively form a trench extending through the masking layers.

Abstract: A method of forming a deep trench in a semiconductor substrate includes: forming a first mask pattern over the semiconductor substrate, in which the first mask pattern has a first opening exposing a portion of the semiconductor substrate; forming a second mask pattern over the first mask pattern, in which the second mask pattern has a second opening substantially aligned with the first opening to expose the portion of the semiconductor substrate, and the second opening has a width greater than a width of the first opening to further expose a portion of the first mask pattern; and removing the portion of the semiconductor substrate, the portion of first mask pattern and another portion of the semiconductor substrate beneath the portion of the first mask pattern to form the deep trench.

Abstract: The present disclosure provides a substrate structure for a micro electro mechanical system (MEMS) device. The substrate structure includes a cap and a micro electro mechanical system (MEMS) substrate. The cap has a cavity, and the MEMS substrate is disposed on the cap. The MEMS substrate has a plurality of through holes exposing the cavity, and an aspect ratio of the through hole is greater than 30.

Abstract: The present disclosure relates to a method of forming a masking structure having a trench with a high aspect ratio, and an associated structure. In some embodiments, the method is performed by forming a first material over a substrate. The first material is selectively etched and a second material is formed onto the substrate at a position abutting sidewalls of the first material, resulting in a pillar of sacrificial material surrounded by a masking material. The pillar of sacrificial material is removed, resulting in a masking layer having a trench that extends into the masking material. Using the pillar of sacrificial material during formation of the trench allows the trench to have a high aspect ratio. For example, the sacrificial material allows for a plurality of masking layers to be iteratively formed to have laterally aligned openings that collectively form a trench extending through the masking layers.

Abstract: A control device which is in communication with a switch comprises a memory which stores applications. The applications can handle received data streams of the switch. The control device selects first applications from all the applications and transmits the first applications and a command to the switch to install the first applications. The switch itself transmits received data streams to the first applications for processing when external data streams are received.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack structure and a second gate stack structure on a substrate, and the first gate stack structure includes a first spacer adjacent to the second gate stack structure. The method also includes forming an U-shaped capping layer between the first gate stack structure and the second gate stack structure, and a lateral sidewall of the U-shaped capping layer is in direct contact with the first spacer of the first gate stack structure. A top of the lateral sidewall of the U-shaped capping layer is below a top of the first spacer of the first gate stack structure.

Abstract: In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate, and the substrate has a cell region and a logic region. The semiconductor device structure also includes an isolation feature formed in the substrate and a first gate stack structure formed on the isolation feature and at the cell region. The semiconductor device structure further includes a second gate stack structure formed on the isolation feature and at the cell region, and the first gate stack structure is adjacent to the second gate stack structure. The isolation feature between the first gate stack structure and the second gate stack structure has a substantially planar topography.

Abstract: A defect inspection apparatus is disclosed that includes a stage, a photosensitive element, and a controller. The stage can support a semiconductor element that has a plurality of complete dies and partial dies surrounding the complete dies. The photosensitive element is located above the stage. The controller is electrically connected to the photosensitive element to drive the photosensitive element to inspect the defects of the complete dies and the partial dies.

Abstract: A method of generating a set of defect candidates for a wafer is disclosed. The wafer comprises at least one die manufactured according to a mask, and the mask being prepared by combining a plurality of layout areas. The method includes receiving an initial defect information from a wafer scanning device indicating potential defects of a semiconductor wafer and determining a boundary region on the semiconductor wafer. The method further includes creating an exclusion region from the boundary region, the exclusion region having a first set of defects in the potential defects of the semiconductor wafer, and creating filtered defect information by removing the first set of defects from the initial defect information.

Abstract: Embodiments of mechanisms of forming a semiconductor device structure are provided. The method includes providing a substrate, forming a first material layer on the substrate, forming a second material layer on the first material layer and forming a first PR layer on the second material layer. The method includes exposing a portion of the first PR layer to a first radiation beam and forming a second PR layer on the first PR layer. The method includes exposing a portion of the second PR layer to a second radiation beam and developing the first PR layer and the second PR layer to form a patterned first PR layer and a patterned second PR layer. The method includes etching a portion of the first material layer and the second material layer by using the patterned first PR layer and the patterned second PR layer as a mask.

Abstract: In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate, and the substrate has a cell region and a logic region. The semiconductor device structure also includes an isolation feature formed in the substrate and a first gate stack structure formed on the isolation feature and at the cell region. The semiconductor device structure further includes a second gate stack structure formed on the isolation feature and at the cell region, and the first gate stack structure is adjacent to the second gate stack structure. The isolation feature between the first gate stack structure and the second gate stack structure has a substantially planar topography.

Abstract: A method of generating a set of defect candidates for a wafer includes generating a filtration area according to a graph operation of one or more of a plurality of layout areas. The wafer includes at least one die manufactured according to a mask, and the mask is prepared by combining the plurality of layout areas. The method further includes generating the set of defect candidates by omitting a subset of initial defect candidates having positions within the filtration area.