Patents by Inventor Tsung-Yuan Yu

Tsung-Yuan Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Capacitor in post-passivation structures and methods of forming the same
    Patent number: 9786591
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen
  • Inductor System and Method
    Publication number: 20170243820
    Abstract: A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed.
    Type: Application
    Filed: May 8, 2017
    Publication date: August 24, 2017
    Inventors: Hsien-Wei Chen, Hung-Yi Kuo, Hao-Yi Tsai, Tsung-Yuan Yu
  • Ball Height Control in Bonding Process
    Publication number: 20170236797
    Abstract: A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package component to the second package component. At least one ball-height control stud separates the first package component and the second package component from each other, and defines a standoff distance between the first package component and the second package component.
    Type: Application
    Filed: May 2, 2017
    Publication date: August 17, 2017
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Jie Chen
  • SYSTEM AND METHOD FOR AN IMPROVED INTERCONNECT STRUCTURE
    Publication number: 20170186713
    Abstract: Presented herein are an interconnect structure and method for forming the same. The interconnect structure includes a contact pad disposed over a substrate and a connector disposed over the substrate and spaced apart from the contact pad. A passivation layer is disposed over the contact pad and over connector, the passivation layer having a contact pad opening, a connector opening, and a mounting pad opening. A post passivation layer including a trace and a mounting pad is disposed over the passivation layer. The trace may be disposed in the contact pad opening and contacting the mounting pad, and further disposed in the connector opening and contacting the connector. The mounting pad may be disposed in the mounting pad opening and contacting the opening. The mounting pad may be separated from the trace by a trace gap, which may optionally be at least 10 ?m.
    Type: Application
    Filed: March 16, 2017
    Publication date: June 29, 2017
    Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu, Tsung-Yuan Yu
  • Ball height control in bonding process
    Patent number: 9679868
    Abstract: A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package component to the second package component. At least one ball-height control stud separates the first package component and the second package component from each other, and defines a standoff distance between the first package component and the second package component.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Jie Chen
  • Packaging devices, methods of manufacture thereof, and packaging methods
    Patent number: 9673160
    Abstract: Packaging devices, methods of manufacture thereof, and packaging methods are disclosed. In some embodiments, a packaging device includes a first substrate including a post passivation interconnect (PPI) structure including a PPI pad disposed thereon, and a second substrate including a contact pad disposed thereon. A conductive bump is coupled between the PPI pad and the contact pad. A molding material is disposed over portions of the PPI structure proximate the conductive bump. A top surface of the molding material contacts the conductive bump at a height of the conductive bump having a width C, and the contact pad has a width B. A ratio R of C:B comprises about 1.0 or greater.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu
  • Methods and Apparatus of Guard Rings for Wafer-Level-Packaging
    Publication number: 20170141051
    Abstract: A method of forming a semiconductor device includes forming a passivation layer on top of a guard ring and an active area of a circuit device, forming a passivation contact within the passivation layer, the passivation contact being over and electrically connected to the guard ring, forming a post-passivation interconnect (PPI) guard ring over the passivation layer and electrically connected to the passivation contact, and forming a first polymer layer over the PPI guard ring, the first polymer layer extending along a sidewall of the PPI guard ring.
    Type: Application
    Filed: January 30, 2017
    Publication date: May 18, 2017
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen
  • Inductor system and method
    Patent number: 9647054
    Abstract: A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tsung-Yuan Yu
  • System and method for an improved interconnect structure
    Patent number: 9633870
    Abstract: Presented herein are an interconnect structure and method for forming the same. The interconnect structure comprises a contact pad disposed over a substrate and a connector disposed over the substrate and spaced apart from the contact pad. A passivation layer is disposed over the contact pad and over connector, the passivation layer having a contact pad opening, a connector opening, and a mounting pad opening. A post passivation layer comprising a trace and a mounting pad is disposed over the passivation layer. The trace may be disposed in the contact pad opening and contacting the mounting pad, and further disposed in the connector opening and contacting the connector. The mounting pad may be disposed in the mounting pad opening and contacting the opening. The mounting pad may be separated from the trace by a trace gap, which may optionally be at least 10 ?m.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu, Tsung-Yuan Yu
  • Packaging devices and methods of manufacture thereof
    Patent number: 9633963
    Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A second portion of the contact pad is exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a hollow region.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu
  • Interconnect structures and methods of forming same
    Patent number: 9589862
    Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an interconnect structure, the method including forming a first post-passivation interconnect (PPI) over a first substrate, forming a second PPI over the first substrate, and forming a first conductive connector on the first PPI. The method further includes forming a second conductive connector on the second PPI, and forming a molding compound on top surfaces of the first and second PPIs and surrounding portions of the first and second connectors, a first section of molding compound being laterally between the first and second connectors, the first section of molding compound having a curved top surface.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: March 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsuan-Ting Kuo, Tsung-Yuan Yu, Hsien-Wei Chen, Wen-Hsiung Lu, Ming-Da Cheng, Chung-Shi Liu
  • Semiconductor device and manufacturing method thereof
    Patent number: 9589915
    Abstract: A semiconductor device includes a substrate defined with a seal ring region and a circuit region, the substrate includes a seal ring structure and an integrated circuit structure, the seal ring structure is disposed in the seal ring region and includes a plurality of stacked conductive layers interconnected by a plurality of via layers, the integrated circuit structure is disposed in the circuit region and includes an active or a passive device; a metal pad disposed over the seal ring region and contacted with the seal ring structure; a passivation layer disposed over the substrate and covering the metal pad; a polymeric layer disposed over the passivation layer and the circuit region; and a molding disposed over the passivation layer and the polymeric layer, wherein the seal ring structure is covered by the molding.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: March 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsung-Yuan Yu, Hao-Yi Tsai, Chao-Wen Shih, Wen-Hsin Chan, Chen-Chih Hsieh
  • Capacitor in Post-Passivation Structures and Methods of Forming the Same
    Publication number: 20170040256
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Application
    Filed: October 25, 2016
    Publication date: February 9, 2017
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen
  • Methods and apparatus of guard rings for wafer-level-packaging
    Patent number: 9559067
    Abstract: A method of forming a semiconductor device includes forming a passivation layer on top of a guard ring and an active area of a circuit device, forming a passivation contact within the passivation layer, the passivation contact being over and electrically connected to the guard ring, forming a post-passivation interconnect (PPI) guard ring over the passivation layer and electrically connected to the passivation contact, and forming a first polymer layer over the PPI guard ring, the first polymer layer extending along a sidewall of the PPI guard ring.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen
  • Inductor for post passivation interconnect and a method of forming
    Patent number: 9553045
    Abstract: An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Jie Chen, Ying-Ju Chen, Tsung-Yuan Yu
  • 3D package with through substrate vias
    Patent number: 9530759
    Abstract: A package, comprising a substrate having electrical devices disposed at a first side of the substrate, vias extending from the first side of the substrate to a second side of the substrate opposite the first side and metallization layers disposed on the first side of the substrate. Contact pads are disposed over the first metallization layers and a protection layer is disposed over the contact pads. Post-passivation interconnects are disposed over the protection layer and extend to the contact pads through openings in the protection layer. Connectors are disposed on the PPIs and a molding compound extends over the PPIs and around the connectors.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Hung-Yi Kuo, Hao-Yi Tsai, Chao-Wen Shih, Tsung-Yuan Yu, Min-Chien Hsiao
  • SEMICONDUCTOR DEVICES WITH BALL STRENGTH IMPROVEMENT
    Publication number: 20160372435
    Abstract: A semiconductor device includes a contact region over a substrate. The semiconductor device further includes a metal pad over the contact region. Additionally, the semiconductor device includes a post passivation interconnect (PPI) line over the metal pad, where the PPI line is in contact with the metal pad. Furthermore, the semiconductor device includes an under-bump-metallurgy (UBM) layer over the PPI line. Moreover, the semiconductor device includes a plurality of solder balls over the UBM layer, the plurality of solder balls being arranged at some, but not all, intersections of a number of columns and rows of a ball pattern.
    Type: Application
    Filed: September 2, 2016
    Publication date: December 22, 2016
    Inventors: Tsung-Yuan Yu, Hsien-Wei Chen, Ying-Ju Chen, Shih-Wei Liang
  • Inductor System and Method
    Publication number: 20160343794
    Abstract: A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 24, 2016
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tsung-Yuan Yu
  • Packaging Devices, Methods of Manufacture Thereof, and Packaging Methods
    Publication number: 20160329291
    Abstract: Packaging devices, methods of manufacture thereof, and packaging methods are disclosed. In some embodiments, a packaging device includes a first substrate including a post passivation interconnect (PPI) structure including a PPI pad disposed thereon, and a second substrate including a contact pad disposed thereon. A conductive bump is coupled between the PPI pad and the contact pad. A molding material is disposed over portions of the PPI structure proximate the conductive bump. A top surface of the molding material contacts the conductive bump at a height of the conductive bump having a width C, and the contact pad has a width B. A ratio R of C:B comprises about 1.0 or greater.
    Type: Application
    Filed: July 22, 2016
    Publication date: November 10, 2016
    Inventors: Hsien-Wei Chen, Tsung-Yuan Yu
  • Capacitor in post-passivation structures and methods of forming the same
    Patent number: 9490203
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: November 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen