Abstract: The presently described embodiments use a printing process, e.g. a wax printing technique, to pattern a mask layer (such as a soldermask layer) of, for example, a printed circuit. Substantially all other conventional processes in developing soldermask and exposure processes can be maintained. According to the presently described embodiments, each printed circuit will have a unique pattern that matches uniform and non-uniform runout. In one form, the pattern is comprised of wax single drops having a specified gap to make the process transparent to the current industry practice. Furthermore, the single drops can be used for both large and small areas without any development time differences. In at least one form, the wax pattern and the soldermask in the gap are removed during development.

Abstract: A tunable optical cavity can be tuned by relative movement between two reflection surfaces, such as by deforming elastomer spacers connected between mirrors or other light-reflective components that include the reflection surfaces. The optical cavity structure includes an analyte region in its light-transmissive region, and presence of analyte in the analyte region affects output light when the optical cavity is tuned to a set of positions. Electrodes that cause deformation of the spacers can also be used to capacitively sense the distance between them. Control circuitry that provides tuning signals can cause continuous movement across a range of positions, allowing continuous photosensing of analyte-affected output light by a detector.

Abstract: An inhomogeneous optical cavity is tuned by changing its shape, such as by changing reflection surface positions to change tilt angle, thickness, or both. Deformable components such as elastomer spacers can be connected so that, when deformed, they change relative positions of structures with light-reflective components such as mirrors, changing cavity shape. Electrodes can cause deformation, such as electrostatically, electromagnetically, or piezoelectrically, and can also be used to measure thicknesses of the cavity. The cavity can be tuned, for example, across a continuous spectrum, to a specific wavelength band, to a shape that increases or decreases the number of modes it has, to a series of transmission ranges each suitable for a respective light source, with a modulation that allows lock-in with photosensing for greater sensitivity, and so forth.

Abstract: A method of jet-printing smooth micro-scale features is presented. The desired feature prior to being printed is masked by various decimation filters and the decimation is performed at various pitches. The subsequently printed image is then scanned and analyzed to determine the roughness of the lines. The optimum decimation pitch is determined by the feature that exhibits the least amount of droplet spreading and has the lowest edge roughness. The optimum decimation pitch may also be calculated from the material properties and the dynamics of fluids.

Abstract: In the case of printing at high addressability, where the cell size is smaller than the spot size, an image can be decimated in a manner that will limit the large accumulation of printed material. The proper decimation of the image will depend on the spot size, the physics of drop coalescence and the addressability during printing. A simple method of using concentric decimation is disclosed herein to enable this process.

Abstract: A method of printing spots with high spot placement accuracy using print heads with random/unevenly spaced ejector locations and coarse alignment of the multiple print heads. This is performed by accurately determining the spot positions from all the print heads using a vision system and printing at high addressability. The spot placement accuracy will be determined by the addressability as long as the ejected drop position is reproducible and other system errors are negligible.

Abstract: A domino SRAM array restore pulse generation system launches the work decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ck1), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

Abstract: A domino SRAM array restore pulse generation system launches the work decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ck1), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

Abstract: A domino SRAM array restore pulse generation system launches the word decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ckl), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

Abstract: An SRAM design evaluation circuit topology has the gates of the SRAM cell pass Gate Field Effect Transistors (FETs) connected to the cross-coupled gates of the inverter pair of the SRAM cell. This evaluation circuit typology is used in a full cell implementation. A series of full cells are interconnected one to another in a loop to form a ring oscillator. The output of the ring is frequency divided and measured to study the read and write behavior of the cell design. Similarly, half-cells, with the gates of their pass gates grounded, are interconnected one to another to form a ring oscillator, the output of which is frequency divided and measured to help isolate pass gate impact on memory function. The modified SRAM cell topology, connected as a ring oscillator in hardware, can be used to fully characterize an SRAM cell design, without the use of peripheral read/write circuitry.

Abstract: A beam position control system controls a position of a beam directed from a beam source. The beam position control system includes a beam position sensing system that generates one or more satellite beams which are used to determine the position of a main beam. A beam offset computation block determines a relative position of the main beam with respect to a desired main beam position and provides beam offset information to a controller that generates a compensation signal used to adjust the main beam position to the desired main beam position via a beam actuation system.

Abstract: A domino SRAM array restore pulse generation system launches the word decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ckl), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

Abstract: A CMOS decoder with an FET stack coupled to the input node so that when all the inputs are selected, the FET stack is conducting and initially holds the value on the input node, and prevents dipping of the input node voltage.

Abstract: A variable modulator assembly includes a deformable layer adhered to a compliant layer surface, and an n-phase electrode configuration, n>2, adhered to an opposite surface of the compliant layer. A controller is configured to selectively apply a variable signal to the selected electrodes of the electrode configuration. Application of the variable signal causes the deformable layer to reconfigure to an alternated shape having distinct peaks and valleys. The distance between the peaks and valleys being determined by the value of the applied variable signal, wherein the alternated shape travels in a preferred direction. An optical modulating method includes positioning the variable modulator assembly to receive and reflect light from a light source, monitoring the reflected light, and altering the variable signal to maintain a desired output intensity.

Abstract: A variable modulator assembly includes a deformable layer adhered to a compliant layer surface, and an n-phase electrode configuration, n>2, adhered to an opposite surface of the compliant layer. A controller is configured to selectively apply a variable signal to the selected electrodes of the electrode configuration. Application of the variable signal causes the deformable layer to reconfigure to an alternated shape having distinct peaks and valleys. The distance between the peaks and valleys being determined by the value of the applied variable signal, wherein the alternated shape travels in a preferred direction. An optical modulating method includes positioning the variable modulator assembly to receive and reflect light from a light source, monitoring the reflected light, and altering the variable signal to maintain a desired output intensity.

Abstract: An SRAM design evaluation circuit topology has the gates of the SRAM cell pass Gate Field Effect Transistors (FETs) connected to the cross-coupled gates of the inverter pair of the SRAM cell. This evaluation circuit typology is used in a full cell implementation. A series of full cells are interconnected one to another in a loop to form a ring oscillator. The output of the ring is frequency divided and measured to study the read and write behavior of the cell design. Similarly, half-cells, with the gates of their pass gates grounded, are interconnected one to another to form a ring oscillator, the output of which is frequency divided and measured to help isolate pass gate impact on memory function. The modified SRAM cell topology, connected as a ring oscillator in hardware, can be used to fully characterize an SRAM cell design, without the use of peripheral read/write circuitry.

Abstract: A method of efficient code generation for modulo scheduled uncounted loops includes: assigning a given stage predicate to each instruction in each stage, including assigning a given stage predicate to each instruction in each speculative stage; and using the stage predicate to conditionally enable or disable the execution of an instruction during the prologue and epilogue execution.

Abstract: A variable modulator assembly includes an active layer. A deformable layer is in operational contact to a first surface of the active layer, and an electrode configuration consisting of a plurality of electrodes is in operational contact to a second surface of the active layer. A controller is configured to selectively apply a variable signal to the selected electrodes of the electrode configuration. Application of the variable signal causes the deformable layer to reconfigure to an alternated shape having distinct peaks and valleys. The distance between the peaks and valleys being determined by the value of the applied variable signal. In an optical modulating method, a variable modulator assembly is positioned to receive light at the deformable layer from a light source. Activation of an electrode configuration by the controller generates a variable signal, causing electrostatic charges to deform the deformable layer into a pattern corresponding to the activated electrodes.

Abstract: Optimizing compiler performance by applying data speculation within modulo scheduled loops to achieve a higher degree of instruction-level parallelism. The compiler locates a schedule for specifying an order of execution of the instructions and allocates rotating registers for the instruction execution. Based upon the schedule and the register allocation, the compiler determines an initiation interval specifying a number of instruction issue cycles between initiation of successive iterations related to the scheduling of the instructions.

Abstract: A beam position control system controls a position of a beam directed from a beam source. A beam position sensing system, generates one or more satellite beams which are used to determine the position of a main beam. A beam offset computation block is configures to determine a relative position of the main beam to a desired main beam position. Beam offset information is generated by the beam offset computational block, and a controller is configured to receive the beam offset information from the beam offset computation block. A compensation signal, generated by the controller, is designed to adjust the main beam position to the desired main beam position, where a beam actuation system is configured to receive the compensation signal and adjust the main beam position.