Abstract: A variable modulator assembly includes an active layer having a first and second surface. A deformable layer is in operational contact to the first surface of the active layer, and an electrode configuration consisting of a plurality of electrodes is in operational contact to the second surface of the active layer. A controller is configured to selectively apply a variable signal to the selected electrodes of the electrode configuration. Application of the variable signal causes the deformable layer to reconfigure to an alternated shape having distinct peaks and valleys. The distance between the peaks and valleys being determined by the value of the applied variable signal.

Abstract: Systems and methods for improving an optimizing compiler are disclosed. A representative compiler, includes: a translation engine and a low-level instruction optimizer, the low-level instruction optimizer further includes a scheduler and register allocator, the scheduler and register allocator comprising: a minimum initiation interval determiner; a modulo scheduler; a rotating register allocator configured to receive a schedule, allocate and assign rotating registers responsive to modulo schedule, and communicate a status of a set of rotating registers; a static register allocator configured to receive the schedule, allocate and assign scalar variables to a set of scalar registers responsive to the modulo schedule and the status; and a rotating register spiller configured to receive and store interfering variables in a memory.

Abstract: A method of efficient code generation for modulo scheduled uncounted loops includes: assigning a given stage predicate to each instruction in each stage, including assigning a given stage predicate to each instruction in each speculative stage; and using the stage predicate to conditionally enable or disable the execution of an instruction during the prologue and epilogue execution.

Abstract: In a computer having rotating registers, a schedule-assigner for allocating the rotating registers. The scheduler-assigner includes a software-pipelined instruction scheduler that generates a first software-pipelined instruction schedule based on an intermediate representation that has data flow information in SSA form. The scheduler-assigner also includes a rotating register allocator that designates live ranges of loop-variant variables in the first software-pipelined instruction schedule as being allocated to rotating registers, when available. The first software-pipelined instruction schedule may be a modulo schedule. When a rotating register is not available, the software-pipelined instruction scheduler may generate a second software-pipelined instruction schedule having an initiation interval greater than the initiation interval of the first software-pipelined instruction schedule.