Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.

Abstract: Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.

Abstract: A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.

Abstract: Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command dock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal.

Abstract: A duty cycle correction circuit includes a rising edge variable delay circuit and a falling edge variable delay circuit. The variable delay for each delay circuit depends upon an uncorrected duty cycle for an uncorrected clock signal being corrected by the duty cycle correction circuit into a corrected clock signal having a desired duty cycle.

Abstract: Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.

Abstract: Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, and a third electrode formed from a third metal layer, wherein second and third electrodes are spaced farther apart than the first and second electrodes. The capacitor structure also comprises a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third metal layers, wherein the second dielectric layer has a larger thickness than the first dielectric layer. The first electrode is coupled to a first power-supply rail, the third electrode is coupled to a second power-supply rail, and the second power-supply rail has a higher power-supply voltage than the first power-supply rail.

Abstract: Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.

Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

Abstract: A duty cycle correction circuit includes a rising edge variable delay circuit and a falling edge variable delay circuit. The variable delay for each delay circuit depends upon an uncorrected duty cycle for an uncorrected clock signal being corrected by the duty cycle correction circuit into a corrected clock signal having a desired duty cycle.

Abstract: Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.

Abstract: Capacitor, resistor and resistor-capacitor components are described herein. In one embodiment, a die comprises first and second metal interconnect layers in a back end of line (BEOL) of the die, and an insulator between the first and second metal interconnect layers. The die also comprises a metal-insulator-metal (MIM) capacitor embedded in the insulator, the MIM capacitor comprising a first metal plate, a second metal plate, and a dielectric layer between the first and second metal plates. The die further comprises a metal resistor embedded in the insulator, wherein the metal resistor and the first metal plate of the MIM capacitor are formed from a same metal layer. In one example, the dielectric layer may have a higher dielectric constant than the insulator. In another example, the second metal plate of the MIM capacitor may overlap the metal resistor.

Abstract: Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, and a third electrode formed from a third metal layer, wherein second and third electrodes are spaced farther apart than the first and second electrodes. The capacitor structure also comprises a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third metal layers, wherein the second dielectric layer has a larger thickness than the first dielectric layer. The first electrode is coupled to a first power-supply rail, the third electrode is coupled to a second power-supply rail, and the second power-supply rail has a higher power-supply voltage than the first power-supply rail.

Abstract: Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A training signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The training signal is then returned to the SoC, where it may be examined by a closed-loop training engine of the SoC. A training result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop training engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

Abstract: Serial data transmission for dynamic random access memory (DRAM) interfaces is disclosed. Instead of the parallel data transmission that gives rise to skew concerns, exemplary aspects of the present disclosure transmit the bits of a word serially over a single lane of the bus. Because the bus is a high speed bus, even though the bits come in one after another (i.e., serially), the time between arrival of the first bit and arrival of the last bit of the word is still relatively short. Likewise, because the bits arrive serially, skew between bits becomes irrelevant. The bits are aggregated within a given amount of time and loaded into the memory array.

Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

Abstract: Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

Abstract: Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a low-voltage capacitor and a high-voltage capacitor. The low-voltage capacitor comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, a third electrode formed from a third metal layer, a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third electrodes. The high-voltage capacitor comprises a fourth electrode formed from the first metal layer, a fifth electrode formed from the third metal layer, and a third dielectric layer between the fourth and fifth electrodes, wherein the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer.

Abstract: An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.