Abstract: A signal interface circuit has a signal path for communicatively coupling host circuitry to peripheral circuitry of multiple peripherals. Communication signals in the signal path are of a peripheral signal level. The signal path has electronic components adapted for use in communicating signals between the host circuitry and the peripheral circuitry. The electronic components in the signal path have reliability limits less than the peripheral signal level. The configuration of the electronic components in the signal path allow communication of signals at the peripheral signal level.

Abstract: A level shifter has at least one of either a pull up or a pull down circuit. The circuit is made of electronic components with reliability limits less than a maximum signal level output by the level shifter. The level shifter also has a timing circuit coupled to at least on of either the pull up or pull down circuit. The timing circuit controls a time of application of an input signal to at least one of either the pull up or pull down circuit preventing a terminal to terminal signal level experienced by the electronic components exceeding the reliability limits.

Abstract: This disclosure describes a clock circuit for a memory controller. The described circuit uses a processor clock signal to generate an input clock signal for use during write operations to the memory, or to generate a feedback clock signal for use during read operations from the memory. The circuit is particularly applicable to mobile wireless devices that include memories that do not generate a strobe. The clock circuit may comprise a driver in series with a resistor element that generates an input clock signal for input to a memory, and a resistor-capacitor (RC) filter in series with a receiver that generates a feedback clock signal for output from the memory, wherein an input to the RC filter is tapped between the driver and the resistor element.

Abstract: A digital output driver includes a pre-driver and a driver that may be implemented with thin-oxide FETs. The pre-driver generates first and second digital signals based on a digital input signal. The first digital signal has a first voltage range determined by a first (e.g., pad) supply voltage and an intermediate voltage. The second digital signal has a second voltage range determined by a second (e.g., core) supply voltage and circuit ground. The driver receives the first and second digital signals and provides a digital output signal having a third voltage range determined by the first supply voltage and circuit ground. The pre-driver may include a latch and a latch driver. The latch stores the current logic value for the digital input signal. The latch driver writes the logic value to the latch. The latch driver is enabled for a short time duration to write the logic value and is turned off afterward.

Abstract: Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull-down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state.

Abstract: A bus system includes multiple devices and a bus. The bus is connected to each device. Each device may include a type of input/output (I/O) device, such as a random access memory (RAM) or a microprocessor. The bus transfers data between devices. Data of each device may be encoded with a unique orthogonal code. Encoded data of each device may be superimposed onto a bus so as to permit substantially concurrent communication on the bus by each of the devices. Data of each device is decoded by correlating the encoded data with the unique code used to form the encoded data.

Abstract: A digital output driver includes a pre-driver and a driver that may be implemented with thin-oxide FETs. The pre-driver generates first and second digital signals based on a digital input signal. The first digital signal has a first voltage range determined by a first (e.g., pad) supply voltage and an intermediate voltage. The second digital signal has a second voltage range determined by a second (e.g., core) supply voltage and circuit ground. The driver receives the first and second digital signals and provides a digital output signal having a third voltage range determined by the first supply voltage and circuit ground. The pre-driver may include a latch and a latch driver. The latch stores the current logic value for the digital input signal. The latch driver writes the logic value to the latch. The latch driver is enabled for a short time duration to write the logic value and is turned off afterward.

Abstract: This disclosure describes a clock circuit for a memory controller. The described circuit uses a processor clock signal to generate an input clock signal for use during write operations to the memory, or to generate a feedback clock signal for use during read operations from the memory. The circuit is particularly applicable to mobile wireless devices that include memories that do not generate a strobe. The clock circuit may comprise a driver in series with a resistor element that generates an input clock signal for input to a memory, and a resistor-capacitor (RC) filter in series with a receiver that generates a feedback clock signal for output from the memory, wherein an input to the RC filter is tapped between the driver and the resistor element.

Abstract: A main die and a stacked die are included in the same component package. A transmission gate (370) is implemented on the main die, and can be enabled to receive leakage current in a connection (318) between the main die and the stacked die, and to conduct the leakage current to a bonding pad (344) that is accessible external to the package. Thus, the connectivity between the main die and the stacked die can be tested after the dies are packaged. The transmission gate is disabled during high-speed testing and normal operation. The package can also include a multiplexer (364) that is enabled during high-speed testing to input and output test signals at the package level. A direction signal is used to indicate whether test signals are being input to or output from the main die.

Abstract: A main die and a stacked die are included in the same component package. A transmission gate (370) is implemented on the main die, and can be enabled to receive leakage current in a connection (318) between the main die and the stacked die, and to conduct the leakage current to a bonding pad (344) that is accessible external to the package. Thus, the connectivity between the main die and the stacked die can be tested after the dies are packaged. The transmission gate is disabled during high-speed testing and normal operation. The package can also include a multiplexer (364) that is enabled during high-speed testing to input and output test signals at the package level. A direction signal is used to indicate whether test signals are being input to or output from the main die.

Abstract: A main die and a stacked die are included in the same component package. A transmission gate (370) is implemented on the main die, and can be enabled to receive leakage current in a connection (318) between the main die and the stacked die, and to conduct the leakage current to a bonding pad (344) that is accessible external to the package. Thus, the connectivity between the main die and the stacked die can be tested after the dies are packaged. The transmission gate is disabled during high-speed testing and normal operation. The package can also include a multiplexer (364) that is enabled during high-speed testing to input and output test signals at the package level. A direction signal is used to indicate whether test signals are being input to or output from the main die.

Abstract: A break-before-make predriver for disabling a PFET of an output driver before enabling an NFET, and vice versa. The predriver includes an input inverter, two cross-coupled inverters, and output buffers. The predriver provides enhanced break-before-make action through sizing the NFETs larger than the PFETs in the predriver's cross-coupled inverters. The input inverter, the cross-coupled inverters and the first and second output buffers are sized with respect to each other such that substantially equal break before make action is provided on both rising and falling edges. The predriver also includes level-shifting capabilities through a different voltage supply at the PFETs of the cross-coupled inverter. The predriver also includes two data output nodes for connection to the two inputs of an output driver. The predriver provides for tristate action by disabling the signal from the predriver output nodes.

Abstract: An orthogonal data link is provided by a first digital device, a second digital device, and a bus coupling the first digital device to the second digital device. The first digital device has a first transmitter that encodes data of the first device with a first code (e.g., [1,1]), for transmission on the bus. The second device has a second transmitter that encodes data of the second device with a second code (e.g., [0,1] or [1,0]), for transmission on the bus. The first device has a first receiver that renders the second data by (a) multiplying signals of the bus with the second code and (b) integrating over a periodicity of the codes. The second device has a second receiver that renders the first data by (a) multiplying signals of the bus with the first code and (b) integrating over a periodicity of the codes.

Abstract: A bus system includes multiple devices and a bus. The bus is connected to each device. Each device may include a type of input/output (I/O) device, such as a random access memory (RAM) or a microprocessor. The bus transfers data between devices. Data of each device may be encoded with a unique orthogonal code. Encoded data of each device may be superimposed onto a bus so as to permit substantially concurrent communication on the bus by each of the devices. Data of each device is decoded by correlating the encoded data with the unique code used to form the encoded data.