Abstract: Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment, the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.

Abstract: A differential preamplifier includes an active load with adjustable common-mode output level. The active load includes a transistor pair, a resistor pair, and a current source. The transistor load is employed to provide high gain, low offset, and a large bandwidth for the differential preamplifier. The resistor pair and current source are used to increase the common-mode output level of the differential preamplifier and to bias the transistor load. The current source can be varied to provide an adjustable common-mode output level suitable for driving next stage devices. The active load design allows the differential preamplifier to operate using only low power voltage supplies and with small-sized transistors.

Abstract: A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.

Abstract: Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.

Abstract: A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.

Abstract: Interleaved analog to digital converter with compensation for parameter mismatch among individual converters. A reference ADC samples an input signal at substantially the same time instances as an individual converter used in the interleaved ADC. The reference values provided by the reference ADC are compared with the digital codes generated by the converter to generate an error value from which estimates of the gain, DC offset and timing errors are computed using statistical techniques. Timing error thus estimated is used to change the phase of the sampling clock provided to the converter, and the gain and DC offset errors estimated are applied to modify the values of reference voltages applied to the converter, thus compensating for parameter mismatches.

Abstract: A differential preamplifier includes an active load with adjustable common-mode output level. The active load includes a transistor pair, a resistor pair, and a current source. The transistor load is employed to provide high gain, low offset, and a large bandwidth for the differential preamplifier. The resistor pair and current source are used to increase the common-mode output level of the differential preamplifier and to bias the transistor load. The current source can be varied to provide an adjustable common-mode output level suitable for driving next stage devices. The active load design allows the differential preamplifier to operate using only low power voltage supplies and with small-sized transistors.

Abstract: Methods and systems for fully differential frequency doubling include receiving a differential input signal having a first frequency, generating a non-inverted or positive output signal having twice the frequency of the input signal, and generating an inverted or negative version of the positive output signal. The positive and negative output signals form a fully differential output. The duty ratio of the output signals substantially matches a duty ratio of the input signals. Fully differential frequency doubling can be implemented with NMOS and/or PMOS devices. The invention further provides optional circuitry for increasing an output signal level.

Abstract: A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.

Abstract: A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.

Abstract: Methods and systems for fully differential frequency doubling include receiving a differential input signal having a first frequency, generating a non-inverted or positive output signal having twice the frequency of the input signal, and generating an inverted or negative version of the positive output signal. The positive and negative output signals form a fully differential output. The duty ratio of the output signals substantially matches a duty ratio of the input signals. Fully differential frequency doubling can be implemented with NMOS and/or PMOS devices. The invention further provides optional circuitry for increasing an output signal level.

Abstract: A bandgap voltage generator generates an output reference voltage and is configured to operate from a low voltage power supply and consumes low power. The bandgap voltage generator includes a non-cascode current mirror that is directly connected to a power supply input and that produces current mirror outputs in response to the power supply input. A differential amplifier senses two of the current mirror outputs, and generates an output that controls the non-cascode current mirror so that the current mirror outputs produce substantially the same current and voltage at the sensed current mirror outputs. A bandgap core circuit includes first and second bipolar devices that receive the constant current from the two current mirror outputs. The first bipolar device is scaled in size relative to the second bipolar device so as to produce an output voltage at a third current mirror output that is multiple of the characteristic bandgap voltage of the bipolar devices.

Abstract: A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT ”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.

Abstract: Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. The separate timing recovery loops can be used to compensate for timing phase errors in the clock generation circuit that are different for each path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. The separate AGC loops can be used to compensate for gain errors on a path-by-path basis.

Abstract: Digital signal processing based methods and systems for receiving electrical and/or optical data signals include electrical receivers, optical receivers, parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a single path receiver. Alternatively, the present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. The separate timing recovery loops can be used to compensate for timing phase errors in the clock generation circuit that are different for each path.

Abstract: The specification describes MOS transistors for analog functions which have increased output impedance. The increased output impedance is the result of reduced drain depletion width. This is accomplished without adverse effects on other device parameters. The MOS transistor structures have an implant added to the lightly doped drain (LDD) with a conductivity type opposite to that of the LDD and a doping level higher than the channel doping. The added implant confines the spread of the depletion layer and reduces its width. A relatively small confinement results in a significant increase in output impedance of the device, and a corresponding increase in transistor gain.

Abstract: A circuit is designed with a first transconductor circuit (903) with a first input terminal (901) coupled to receive a voltage signal, a second input terminal (1017) coupled to receive a control signal and an output terminal. The first transconductor circuit has a gain responsive to the control signal. A first integrator circuit (905) has an input terminal coupled to the first transconductor circuit output terminal and has an output terminal. A second transconductor circuit (909) has an input terminal coupled to the first integrator circuit output terminal and an output terminal. A second integrator circuit (911) has an input terminal coupled to the second transconductor circuit output terminal and has an output terminal.

Abstract: A feed-forward compensated negative feedback circuit comprises an operational amplifier having an inverting and a non-inverting input and an output. A feedback element is connected between the output of the operational amplifier and its inverting input to form a negative feedback loop. The inverting input of the op-amp is driven with a first transconductance amplifier which produces an output current proportional to an input voltage. A feed-forward transconductance amplifier receives the input voltage and produces an inverted output current proportional to the input voltage. A feed-forward current is injected at the output of the operational amplifier. By providing at the output of the op-amp the current it would be required to carry over the feedback loop, a voltage differential at the op-amp inputs is avoided, thus eliminating parasitic current flows across the parasitic input capacitance and thereby improving the circuits overall performance.

Abstract: A high speed and low power digital circuit for producing an output responsive to a plurality of input data signals, such as a multiplexer or a latch includes one or more data switching elements. Each of the switching elements is a differential transistor pair having one transistor driven by a control signal and the other transistor driven by a data signal. The signal levels for the data and control signals are interleaved so that each control signal turns on and off the effect of the data signal on the current flow in the switching element. The circuit structure avoids emitter coupling more than two transistors at any point in order to reduce the capacitance at critical nodes and consequently increase switching speed. By providing two switching elements with data transistors connected to a common pull-down resistor, two data signals, and a complementary pair of control signals, a multiplexing function can be performed.

Abstract: Two or more equal amplitude periodic output signals which are mutually shifted in phase by an integer fraction of 360 degrees, such as 90°, are generated by injection locking a ring type oscillator circuit arrangement with a periodic low phase noise signal source. More particularly, a first ring oscillator is injection locked by a low phase noise signal source, one having a noise characteristic which meets the GSM radio standard of at least −132 dBc/Hz at a 3 MHz offset. An identical second ring oscillator is then driven with the output of the first ring oscillator. In one circuit configuration, an even numbered, e.g., a four stage ring oscillator is injection locked to a low-phase noise oscillator having a predetermined noise specification which is application specific and wherein a second even numbered stage, e.g., a four stage ring oscillator is coupled to the first ring oscillator. In a second circuit configuration, a first odd numbered, e.g.