Patents by Inventor Vivek K. De

Vivek K. De has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DC-DC CONVERTER SWITCHING TRANSISTOR CURRENT MEASUREMENT TECHNIQUE
    Publication number: 20130271105
    Abstract: A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current.
    Type: Application
    Filed: June 10, 2013
    Publication date: October 17, 2013
    Inventors: Gerhard Schrom, Peter Hazucha, Vivek K. De, Tanay Karnik
  • Circuits and methods for memory
    Patent number: 8488390
    Abstract: Embodiments for data dependent boosted (DDB) bit cells that may allow for smaller minimum cell supplies (Vmin) without necessarily having to increase device dimensions are presented.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: July 16, 2013
    Assignee: Intel Corporation
    Inventors: Jaydeep P. Kulkarni, Dinesh Somasekhar, James W. Tschanz, Vivek K. De
  • Memory write operation methods and circuits
    Patent number: 8467263
    Abstract: In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: June 18, 2013
    Assignee: Intel Corporation
    Inventors: Jaydeep P. Kulkarni, Muhammad M. Khellah, Bibiche M. Geuskens, Arijit Raychowdhury, Tanay Karnik, Vivek K. De
  • MULTIPHASE TRANSFORMER FOR A MULTIPHASE DC-DC CONVERTER
    Publication number: 20130113444
    Abstract: A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
    Type: Application
    Filed: December 26, 2012
    Publication date: May 9, 2013
    Inventors: Gerhard Schrom, Peter Hazucha, Jaeseo Lee, Tanay Karnik, Vivek K. De, Fabrice Paillet
  • CIRCUITS AND METHODS FOR MEMORY
    Publication number: 20130003469
    Abstract: Embodiments for data dependent boosted (DDB) bit cells that may allow for smaller minimum cell supplies (Vmin) without necessarily having to increase device dimensions are presented.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Inventors: Jaydeep P. Kulkarni, Dinesh Somasekhar, James W. Tschanz, Vivek K. De
  • Component reliability budgeting system
    Patent number: 8312306
    Abstract: A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: November 13, 2012
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, James W. Tschanz, Vivek K. De, Stephen H. Tang
  • Power management integrated circuit
    Patent number: 8288846
    Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: October 16, 2012
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, James W. Tschanz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Performing Variation-Aware Profiling And Dynamic Core Allocation For A Many-Core Processor
    Publication number: 20120159496
    Abstract: In one embodiment, the present invention includes a processor with multiple cores each having a self-test circuit to determine a frequency profile and a leakage power profile of the corresponding core. In turn, a scheduler is coupled to receive the frequency profiles and the leakage power profiles and to schedule an application on at least some of the cores based on the frequency profiles and the leakage power profiles. Other embodiments are described and claimed.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 21, 2012
    Inventors: Saurabh Dighe, Sriram R. Vangal, Nitin Y. Borkar, Vivek K. De
  • MEMORY WRITE OPERATION METHODS AND CIRCUITS
    Publication number: 20110317508
    Abstract: In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost.
    Type: Application
    Filed: June 25, 2010
    Publication date: December 29, 2011
    Inventors: JAYDEEP P. KULKARNI, Muhammad M. Khellah, Bibiche M. Geuskens, Arijit Raychowdhury, Tanay Karnik, Vivek K. De
  • Low power serial link bus architecture
    Patent number: 7817068
    Abstract: Embodiments of the present invention provide a bus architecture utilizing multiple-pumped serial links, and a combination of encoding and serialization to two data streams to transmit and receive a serialized data stream over a bus. The order in which encoding and serialization takes place depends upon the anticipated activity factors of the two data streams, and is chosen to reduce average energy dissipation. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: October 19, 2010
    Assignee: Intel Corporation
    Inventors: Maged Ghoneima, Muhammad M. Khellah, Vivek K. De
  • Power management integrated circuit
    Publication number: 20100219516
    Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
    Type: Application
    Filed: February 24, 2010
    Publication date: September 2, 2010
    Inventors: Siva G. Narendra, James W. Tschanz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • COMPONENT RELIABILITY BUDGETING SYSTEM
    Publication number: 20100145895
    Abstract: A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
    Type: Application
    Filed: February 12, 2010
    Publication date: June 10, 2010
    Inventors: Siva G. Narendra, James W. Tschanz, Vivek K. De, Stephen H. Tang
  • CPU POWER DELIVERY SYSTEM
    Publication number: 20100115301
    Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
    Type: Application
    Filed: January 8, 2010
    Publication date: May 6, 2010
    Inventors: Siva G. Narendra, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • CPU power delivery system
    Patent number: 7698576
    Abstract: A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Component reliability budgeting system
    Patent number: 7689845
    Abstract: A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: March 30, 2010
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, James W. Tschanz, Vivek K. De, Stephen H. Tang
  • Method and apparatus for bus repeater tapering
    Patent number: 7684520
    Abstract: A method and apparatus for bus repeater tapering. The sizing of repeaters on a portion of one transmission line is chosen to propagate a signal transition at a particular rate. The sizing of repeaters on a substantially parallel portion of another transmission line, is chosen to propagate a second signal transition at a different rate. Thus, the worst-case capacitance coupling factor between the two transmission lines may be reduced.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: March 23, 2010
    Assignee: Intel Corporation
    Inventors: James W. Tschanz, Muhammad M. Khellah, Yibin Ye, Vivek K. De
  • Power management integrated circuit
    Patent number: 7671456
    Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: March 2, 2010
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, James W. Tschantz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Communications receiver with digital counter
    Patent number: 7620119
    Abstract: A communications receiver includes a digital counter to count transitions of a carrier signal subject to on/off keying.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: November 17, 2009
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, Yatin Hoskote, Saurabh Dighe, Nitin Y. Borkar, Vivek K De
  • Apparatus for power consumption reduction
    Patent number: 7562316
    Abstract: A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block having an edge-triggered circuit may be provided in a second area of the chip. Edge-triggered circuits within the second functional block may be replaced with dual edge-triggered circuits. Phase logic circuits may be clocked by a full frequency clock signal and dual edge-triggered circuits may be clocked by a half-frequency clock signal.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: July 14, 2009
    Assignee: Intel Corporation
    Inventors: James W. Tschanz, Nasser A. Kurd, Javed Barkatullah, Vivek K. De
  • Sense amplifier method and arrangement
    Patent number: 7532528
    Abstract: A memory system having a selectable configuration for sense amplifiers is included. The memory system can include bit cells and a switch module coupled to the bit cell and to a first portion of a sense amplifier. The switch module can connect, disconnect or cross couple the bit cell to the sense amplifier based on a test for the input offset voltage of first portion of the sense amplifier. A similar configuration can be implemented by a second portion of the sense amplifier. The system can also include a programmer module to configure a setting of the switch module and can include a column select module to couple the bit cells to the sense amplifiers based on what column of bit cell is to be read. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 30, 2007
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Dinesh Somasekhar, Muhammad M Khellah, Yibin Ye, Nam Sung Kim, Vivek K De