Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

Abstract: A lighting connector which includes (a) an upper housing having plural connector pins, and one or more interlocking grooves; and (b) a lower housing, the lower housing having a plurality of connector pin guide holes, and one or more interlocking tongue portions. The lower housing is connectable with the upper housing to form the lighting connector by coupling at least one of the one or more interlocking grooves with at least one of the one or more interlocking tongue portions, and by coupling at least one of the plural connector pins with at least one of the connector pin guide holes.

Abstract: Methods and systems selectively irradiate structures on or within a semiconductor substrate using a plurality of laser beams. The structures are arranged in a row extending in a generally lengthwise direction. The method generates a first laser beam that propagates along a first laser beam axis that intersects the semiconductor substrate and a second laser beam that propagates along a second laser beam axis that intersects the semiconductor substrate. The method simultaneously directs the first and second laser beams onto distinct first and second structures in the row. The method moves the first and second laser beam axes relative to the semiconductor substrate substantially in unison in a direction substantially parallel to the lengthwise direction of the row, so as to selectively irradiate structures in the row with one or more of the first and second laser beams simultaneously.

Abstract: A modular luminaire which uses LED light sources. The basic frame comprises two end pieces compressed together by through bolts. At least one elongated heat sink is compressed between the end pieces. Each heat sink may bear a plurality of LEDs mounted on a printed circuit board which may have an integral metallic backplate, and is installed on one of the heat sinks with a layer of heat conductive grease therebetween. The heat sinks have fins projecting in three directions, the fourth direction being accounted for by the LEDs, and are rotatable about their longitudinal axes to adjust direction of light propagation. The heat sinks are arrayed in an arc, so that the outside heat sinks shield observers from direct glare from opposed heat sinks. Heat sinks may be extruded to form cooling fins and slots which may receive fasteners such as screws.

Abstract: A system determines relative positions of a semiconductor substrate and a plurality of laser beam spots on or within the semiconductor substrate in a machine for selectively irradiating structures on or within the substrate using a plurality of laser beams. The system comprises a laser source, first and second laser beam propagation paths, first and second reflection sensors, and a processor. The laser source produces at least the first and second laser beams, which propagate toward the substrate along the first and second propagation paths, respectively, which have respective first and second axes that intersects the substrate at respective first and second spots. The reflection sensors are positioned to detect reflection of the spots, as the spots moves relative to the substrate, thereby generating reflection signals. The processor is configured to determine, based on the reflection signals, positions of the spots on or within the substrate.

Abstract: A modular luminaire which uses LED light sources. The basic frame comprises two end pieces compressed together by through bolts. At least one elongated heat sink is compressed between the end pieces. Each heat sink may bear a plurality of LEDs mounted on a printed circuit board which may have an integral metallic backplate, and is installed on one of the heat sinks with a layer of heat conductive grease therebetween. The heat sinks have fins projecting in three directions, the fourth direction being accounted for by the LEDs, and are rotatable about their longitudinal axes to adjust direction of light propagation. The heat sinks are arrayed in an arc, so that the outside heat sinks shield observers from direct glare from opposed heat sinks. Heat sinks may be extruded to form cooling fins and slots which may receive fasteners such as screws.

Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

Abstract: The present invention provides in an adjustable shower head having a user-operable variable spray pattern. The shower head includes an adjustment mechanism that is hydropowered by water passing through the shower head, upon activation by a user.

Abstract: Methods and systems for generating masks for spacer formation are disclosed. As a part of a disclosed method, a predefined final wafer pattern is accessed, areas related to features in the predefined final wafer pattern are identified and a template mask is formed based on the identified areas for forming spacers on a wafer. Subsequently, a mask is formed for use in the removal of portions of the spacers to form an on wafer pattern that corresponds to the predefined final wafer pattern.

Abstract: Methods and systems selectively irradiate structures on or within a semiconductor substrate using a plurality of pulsed laser beams. The structures are arranged in a row extending in a generally lengthwise direction. The method generates a first pulsed laser beam that propagates along a first laser beam axis that intersects the semiconductor substrate and a second pulsed laser beam that propagates along a second laser beam axis that intersects the semiconductor substrate. The method directs respective first and second pulses from the first and second pulsed laser beams onto distinct first and second structures in the row. The method moves the first and second laser beam axes relative to the semiconductor substrate substantially in unison in a direction substantially parallel to the lengthwise direction of the row.

Abstract: A system for forming two laser processing beams with controlled stability at a target specimen work surface includes first and second mutually coherent laser beams propagating along separate first and second beam paths that are combined to perform an optical property adjustment. The combined laser beams are separated into third and fourth laser beams propagating along separate beam paths and including respective third and fourth main beam components, and one of the third and fourth laser beams contributes a leakage component that copropagates in mutual temporal coherence with the main beam component of the other of the third and fourth laser beams. An effect of mutual temporal coherence of the leakage component and the other main beam component with which the leakage component copropagates is reduced through acousto-optic modulation frequency shifts or through incorporation of an optical path length difference in the two beams.

Abstract: The present invention is directed to methods of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a high-K dielectric material assisted with an ion beam to enable the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric films have a high degree of crystallographic alignment at grain boundaries. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The result is a dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.

Abstract: Methods and systems selectively irradiate structures on or within a semiconductor substrate using a plurality of laser beams. The structures are arranged in a row extending in a generally lengthwise direction. The method generates a first laser beam that propagates along a first laser beam axis that intersects the semiconductor substrate and a second laser beam that propagates along a second laser beam axis that intersects the semiconductor substrate. The method directs the first and second laser beams onto non-adjacent first and second structures in the row. The method moves the first and second laser beam axes relative to the semiconductor substrate along the row substantially in unison in a direction substantially parallel to the lengthwise direction of the row.

Abstract: Methods and systems selectively irradiate structures on or within a semiconductor substrate using a plurality of pulsed laser beams. The structures are arranged in a row extending in a generally lengthwise direction. The method generates a first pulsed laser beam that propagates along a first laser beam axis that intersects the semiconductor substrate and a second pulsed laser beam that propagates along a second laser beam axis that intersects the semiconductor substrate. The method directs respective first and second pulses from the first and second pulsed laser beams onto distinct first and second structures in the row. The method moves the first and second laser beam axes relative to the semiconductor substrate substantially in unison in a direction substantially parallel to the lengthwise direction of the row.

Abstract: A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line.

Abstract: A method of and system for forming two laser processing beams with controlled stability at a target specimen work surface includes first and second mutually coherent laser beams propagating along separate first and second beam paths that are combined to perform an optical property adjustment. The combined laser beams are separated into third and fourth laser beams propagating along separate beam paths and including respective third and fourth main beam components, and one of the third and fourth laser beams contributes a leakage component that copropagates in mutual temporal coherence with the main beam component of the other of the third and fourth laser beams. An effect of mutual temporal coherence of the leakage component and the other main beam component with which the leakage component copropagates is reduced through acousto-optic modulation frequency shifts or through incorporation of an optical path length difference in the two beams.

Abstract: Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing exposed portions of a first poly layer while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing exposed portions of a charge storage layer while leaving portions of the charge storage layer protected by the two split sub-lithographic first poly gates, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.

Abstract: A lighting connector which includes (a) an upper housing having plural connector pins, and one or more interlocking grooves; and (b) a lower housing, the lower housing having a plurality of connector pin guide holes, and one or more interlocking tongue portions. The lower housing is connectable with the upper housing to form the lighting connector by coupling at least one of the one or more interlocking grooves with at least one of the one or more interlocking tongue portions, and by coupling at least one of the plural connector pins with at least one of the connector pin guide holes.

Abstract: A method of replacing a top oxide around a storage element of a memory device is provided. The method can involve removing a core first poly and core first top oxide in a core region while not removing a periphery first poly in a periphery region on a semiconductor substrate; forming a second top oxide around a storage element in the core region and on the periphery first poly in the periphery region; forming a second poly over the semiconductor substrate in both the core and periphery regions; removing the second poly and second top oxide in the periphery region; and forming a third poly on the semiconductor substrate in both the core and periphery regions.

Abstract: A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line.