Abstract: A new architecture for implementing a digital algorithm such as a decimation algorithm is described. The new decimator circuit is well suited for digital circuits such as a delta-sigma (or sigma-delta) analog-to-digital converter. In particular, the new decimator circuit incorporates a general purpose architecture which enables a wide range of flexibility to change and modify the decimation algorithm performed by the decimator circuit. Moreover, the new decimator circuit can be fabricated in a smaller chip area than previously possible.

Abstract: The present invention relates to a band-gap reference circuit. The circuit comprises a plurality of diodes connected in series in one or more chains, a current source to flow current through the diode chains, and a selection of shunt current sources. The shunt current sources are connected in parallel with the main current sources and each, or any, can be selected in order to add current to the diode chain. In this manner, current flow through the diode chain is adjusted in order to provide a trimmable band-gap reference voltage. By adjusting the current flow, the high precision reference voltage circuit can provide a very accurate reference value for variations in process state, process error and temperature.

Abstract: A new digital configurable macro architecture is described. The digital configurable macro architecture is well suited for microcontroller or controller designs. In particular, the foundation of the digital configurable macro architecture is a programmable digital circuit block. The programmable digital circuit blocks can be configured to coupled in series or in parallel to handle more complex digital functions. More importantly, the configuration of the programmable digital circuit block is determined by its small number of configuration registers. This provides much flexibility. In particular, the configuration of the programmable digital circuit block is fast and easy since changes in configuration are accomplished by changing the contents of the configuration registers, whereas the contents are generally a small number of configuration data bits.

Abstract: The present invention relates to an input/output node in an electronic device which comprises an input/output pin, a plurality of programmable pull-up resistors and a plurality of programmable pull-down resistors. Each of the pull-up and pull-down resistors, or a combination of them, can be activated by turning on or off n-MOS and p-MOS transistors with logic contained in a mode register. The pull-up and pull-down resistance can be implemented by the inclusion of a resistor in series or by utilization of the innate resistance of the MOS-FET transistor, itself. The resistances can be strong, medium, or weak, depending on the needs of the circuitry. One advantage of such control over drive strength is the ability to transmit or receive data in virtually any electronic environment. Another advantage is the ability to reduce voltage ramp-rates, which reduces high frequency harmonics and the attendant electromagnetic interference.

Abstract: A method and a system for supplying power to a microcontroller with a single cell battery. A power supply pump circuit may be incorporated with the microcontroller having dynamic interaction. The microcontroller sends its power requirements to the power supply pump circuit and in response, the power supply pump circuit controls the operating voltage with optimal efficiency. The dynamic update of power supply pump circuit results in an efficient use of the power supply pump circuit and thus results in a reduction of the number of dry cell batteries to only a single cell. Incorporation of the microcontroller and power supply pump circuit onto a single chip reduces the pin number requirements as well as the space required on the printed circuit board.

Abstract: An oscillator circuit configured to generate an output signal having a frequency comprising a current source, a trim circuit, and one or more capacitors. The current source may be configured to generate a temperature independent current in response to a first adjustment signal. The trim circuit may be configured to generate the first adjustment signal. The one or more capacitors may be configured to charge to a controlled voltage using the temperature independent current. The controlled voltage may regulate a variation of the frequency of the output signal.

Abstract: A new digital configurable macro architecture is described. The digital configurable macro architecture is well suited for microcontroller or controller designs. In particular, the foundation of the digital configurable macro architecture is a programmable digital circuit block. In an embodiment, programmable digital circuit blocks are 8-bit circuit modules that can be programmed to perform any one of a variety of predetermined digital functions by changing the contents of a few registers therein, unlike a FPGA which is a generic device that can be programmed to perform any arbitrary digital function. Specifically, the circuit components of the programmable digital circuit block are designed for reuse in several of the predetermined digital functions such that to minimize the size of the programmable digital circuit block.

Abstract: Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Abstract: A circuit comprising a memory array having a first region, a second region, a plurality of bitlines and an X-decoder. A plurality of transistors may each coupled between the first and second regions, where each of the transistors may be configured to (i) separate the first and the second region during a read operation and (ii) join the first and the second region during a write operation. Alternatively, a plurality of memory regions may be implemented, each separated by another plurality of transistors.

Abstract: A circuit including an oscillator circuit, a current generator circuit and a voltage generator circuit. The oscillator circuit may be configured to generate an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal. The current generator may be configured to generate said first control signal in response to a first adjustment signal. The voltage generator circuit may be configured to generate the second control signal in response to a second adjustment signal.

Abstract: An expandable ECL matrix shifter is provided to have very few interconnecting wires. The shifter can perform a multicolumn right shift or a multicolumn left shift in one cycle, and it has independent wrap and fill capabilities. Two 2 to 1 multiplexers are provided for each bit position of the input signals. The input signals provide one of the inputs for both of the multiplexers. The second input of each multiplexer is a signal indicating what type of fill is desired. The shifter has horizontal data input lines, vertical data output lines, and diagonal select lines. A bipolar transistor is located at each intersection of a data input line and a data output line. These transistors selectively connect the data input lines to the data output lines in response to signals on the diagonal select lines. Each horizontal data input line is divided into two parts. The division of the data input lines into parts is along a major diagonal of the matrix.