Patents by Inventor Wataru Nakamura

Wataru Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150204946
    Abstract: A deposition detection circuit (3) provided in a deposition detection device (1) includes a determination circuit (4) determines whether the movable contact (9) is deposited based on a step input signal and a transient response signal when a drive signal is in an off state. The transient response signal is generated so as to correspond to voltage less than or equal to operating voltage of the electromagnetic relay switch (5) according to an excitation coil (6) and a fixed resistor (R1).
    Type: Application
    Filed: July 8, 2013
    Publication date: July 23, 2015
    Applicant: OMRON CORPORATION
    Inventors: Masahiro Kinoshita, Hiroyuki Iwasaka, Wataru Nakamura
  • Publication number: 20150200068
    Abstract: A unit for controlling one or more electromagnetic relays, each having a contact point and an exciting coil to which rated power is supplied so as to open and close the contact point, has a control circuit which carries out PWM control so as to keep an electromagnetic relay turned on, after turning on the electromagnetic relay by causing rated power to be supplied to an exciting coil of the electromagnetic relay, and a temperature detecting circuit that detects a resistance value of the exciting coil so as to allow the control circuit to calculate a temperature of the electromagnetic relay. The control circuit changes, depending on external information, a controlling value in accordance with which the PWM control is carried out with respect to the electromagnetic relay. The control circuit detects, from the temperature detecting circuit, a voltage corresponding to the resistance value of the exciting coil.
    Type: Application
    Filed: July 8, 2013
    Publication date: July 16, 2015
    Inventors: Masahiro Kinoshita, Hiroyuki Iwasaka, Wataru Nakamura
  • Patent number: 9070600
    Abstract: A drain electrode (17) includes (i) a lower drain electrode (17a) stacked on a semiconductor layer (14) so as to partially cover an upper surface of the semiconductor layer (14) and (ii) an upper drain electrode (17b). The semiconductor layer (14), the lower drain electrode (17a), and the upper drain electrode (17b) form steps. In a step part where the steps are formed, a distance between a periphery of the lower drain electrode (17a) and a periphery of the upper drain electrode (17b) is more than 0.4 ?m but less than 1.5 ?m.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: June 30, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiromitsu Katsui, Yoshimasa Chikama, Wataru Nakamura, Tetsunori Tanaka, Kenichi Kitoh
  • Publication number: 20150152243
    Abstract: TASK It is an object of the present invention to provide a hydrogel having excellent mechanical properties and capable of being produced simply by using and mixing an industrially easily obtainable polymer having high versatility and clay particles, and to provide a method of producing the hydrogel. MEANS OF SOLVING THE PROBLEM A hydrogel-forming composition is characterized by containing a polyelectrolyte (A), clay particles (B), and a dispersant (C) for the clay particles.
    Type: Application
    Filed: January 8, 2015
    Publication date: June 4, 2015
    Applicant: National University Corporation Gunma University
    Inventors: Hiroyuki TAKENO, Wataru NAKAMURA
  • Publication number: 20150126665
    Abstract: TASK It is an object of the present invention to provide a hydrogel having excellent mechanical properties and capable of being produced simply by using and mixing an industrially easily obtainable polymer having high versatility and clay particles, and to provide a method of producing the hydrogel. MEANS OF SOLVING THE PROBLEM A hydrogel-forming composition is characterized by containing a polyelectrolyte (A), clay particles (B), and a dispersant (C) for the clay particles.
    Type: Application
    Filed: January 8, 2015
    Publication date: May 7, 2015
    Inventors: Hiroyuki TAKENO, Wataru NAKAMURA
  • Publication number: 20150115780
    Abstract: In one embodiment, a generator includes an alternating current exciter to output first, second and third alternating currents respectively having first, second and third phases, and a rotary rectifier to convert the first, second and third alternating currents into first, second and third direct currents, respectively. The generator further includes a rotating shaft on which the exciter and the rectifier are mounted, and plural conductors mounted on the shaft, and including one or more first conductors, one or more second conductors and one or more third conductors to respectively supply the first, second and third alternating currents from the exciter to the rectifier. The plural conductors include one or more conductor groups in each of which two or more conductors are collectively arranged, and each of the conductor groups includes the two or more conductors arranged to cancel a magnetic field around each conductor in the same group.
    Type: Application
    Filed: July 8, 2014
    Publication date: April 30, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenmei SHIMANUKI, Hidetoshi SUGIMURA, Toru OTAKA, Daisuke HIRAMATSU, Kazuma TSUJIKAWA, Wataru NAKAMURA, Kazuki SATO, Kunitomi NIIDA, Yutaro ARAI, Keiichiro KIMURA
  • Patent number: 8980121
    Abstract: The present invention provides an etching liquid for a multilayer thin film containing a copper layer and a titanium layer, and a method of using it for etching a multilayer thin film containing a copper layer and a titanium layer, that is, an etching liquid for a multilayer thin film containing a copper layer and a titanium layer, which comprises (A) hydrogen peroxide, (B) nitric acid, (C) a fluoride ion source, (D) an azole, (E) a quaternary ammonium hydroxide and (F) a hydrogen peroxide stabilizer and has a pH of from 1.5 to 2.5, and a etching method of using it.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: March 17, 2015
    Assignees: Mitsubishi Gas Chemical Company, Inc., Sharp Kabushiki Kaisha
    Inventors: Tomoyuki Adaniya, Satoshi Okabe, Toshiyuki Gotou, Taketo Maruyama, Kazuki Kobayashi, Keiichi Tanaka, Wataru Nakamura, Kenichi Kitoh, Tetsunori Tanaka
  • Patent number: 8962742
    Abstract: A hydrogel having mechanical properties and capable of being produced simply by using and mixing an industrially obtainable polymer having high versatility and clay particles, and to provide a method of producing the hydrogel. A hydrogel-forming composition is characterized by containing a polyelectrolyte, clay particles, and a dispersant for the clay particles.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: February 24, 2015
    Assignee: National University Corporation Gunma University
    Inventors: Hiroyuki Takeno, Wataru Nakamura
  • Patent number: 8957145
    Abstract: A hydrogel having excellent mechanical properties and capable of being produced simply by using and mixing an industrially easily obtainable polymer having high versatility and clay particles, and to provide a method of producing the hydrogel. A hydrogel-forming composition is characterized by containing a polyelectrolyte, clay particles, and a dispersant for the clay particles.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 17, 2015
    Assignee: National University Corporation Gunma University
    Inventors: Hiroyuki Takeno, Wataru Nakamura
  • Patent number: 8779430
    Abstract: A semiconductor device (18) includes: a gate electrode (102) formed on a substrate (101); a semiconductor layer (104) formed above the gate electrode (102) and including a source region, a drain region, and a channel region; a source electrode (106) connected to the source region above the semiconductor layer (104); and a drain electrode (107) connected to the drain region above the semiconductor layer (104). The semiconductor layer (104) has, at a portion overlapping the drain electrode (107), a protrusion that protrudes outward along an extending direction of a drain line drawn out from the drain electrode (107). At an outside of the channel region sandwiched between the drain electrode (107) and the source electrode (106), the semiconductor layer (104) has an adjustment portion where an outer boundary of the semiconductor layer (104) is positioned more inward than an outer boundary of the gate electrode (102).
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: July 15, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shoji Okazaki, Takeshi Yaneda, Wataru Nakamura, Hiromitsu Katsui
  • Patent number: 8779296
    Abstract: A wiring board is provided which can prevent a metal electrode from corroding due to a defect in a transparent conductive electrode covering an end face of an organic insulating film. An active-matrix substrate includes: a glass substrate; a metal wire provided on the glass substrate; a gate insulating film covering the metal wire; an interlayer insulating film covering the gate insulating film; and a transparent electrode formed on the interlayer insulating film. The scanning wire provided with a terminal area where the transparent electrode is laminated directly on the scanning wire. The transparent electrode extends over the terminal area in such a way as to cover an end face of the interlayer insulating film that faces the terminal area and an end face of the gate insulating film that faces the terminal area.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: July 15, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiromitsu Katsui, Kenichi Kitoh, Wataru Nakamura
  • Patent number: 8729612
    Abstract: An active matrix substrate includes a plurality of scanning lines (11a) extending parallel to each other; a plurality of signal lines (16a) extending parallel to each other in a direction crossing the scanning lines (11a); a plurality of TFTs (5) each provided at each of intersections of the scanning lines (11a) and the signal lines (16a), and each including a semiconductor layer (4a); and a coating type insulating layer formed between each of the scanning lines (11a) and each of the signal lines (16a). A plurality of openings (15a) are formed in the insulating layer such that each of the semiconductor layers (4a) is exposed, and at least part of a peripheral end of the opening (15a) of the insulating layer is positioned on an inner side relative to each of peripheral ends of the semiconductor layers (4a).
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: May 20, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiromitsu Katsui, Wataru Nakamura
  • Patent number: 8711296
    Abstract: An active matrix substrate (30) of the present invention includes a substrate, a gate line (50) formed on the substrate, and an interlayer insulating layer (90) for insulating a layer formed on the gate line (50) from the gate line (50). In a region of the substrate, the interlayer insulating layer (90) is not provided on an upper surface of the gate line (50), and therefore, the upper surface is exposed. On the other hand, the insulating layer (90) is provided on the substrate so as to have contact with at least an edge face of the gate line (50) which edge face is on an extension of a longitudinal direction of the gate line (50).
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: April 29, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsunori Tanaka, Atsushi Ban, Tohru Senoo, Wataru Nakamura, Yukimine Shimada
  • Publication number: 20140080956
    Abstract: A hydrogel having mechanical properties and capable of being produced simply by using and mixing an industrially obtainable polymer having high versatility and clay particles, and to provide a method of producing the hydrogel. A hydrogel-forming composition is characterized by containing a polyelectrolyte, clay particles, and a dispersant for the clay particles.
    Type: Application
    Filed: May 15, 2013
    Publication date: March 20, 2014
    Inventors: Hiroyuki TAKENO, Wataru NAKAMURA
  • Publication number: 20140014952
    Abstract: A drain electrode (17) includes (i) a lower drain electrode (17a) stacked on a semiconductor layer (14) so as to partially cover an upper surface of the semiconductor layer (14) and (ii) an upper drain electrode (17b). The semiconductor layer (14), the lower drain electrode (17a), and the upper drain electrode (17b) form steps. In a step part where the steps are formed, a distance between a periphery of the lower drain electrode (17a) and a periphery of the upper drain electrode (17b) is more than 0.4 ?m but less than 1.5 ?m.
    Type: Application
    Filed: January 31, 2012
    Publication date: January 16, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Hiromitsu Katsui, Yoshimasa Chikama, Wataru Nakamura, Tetsunori Tanaka, Kenichi Kitoh
  • Publication number: 20130297820
    Abstract: A traffic data integration method includes: obtaining, by using a computer, pieces of frame data having a same data pattern between first and second traffic data collected respectively by first and second capture devices that capture, as traffic data, frame data communicated by a node in a network; performing, by using the computer, a time correction process by which a time of each piece of frame data in the first and second traffic data is corrected so that capturing times of pieces of obtained frame data are identical; using, by using the computer, frame data for which a same data pattern does not appear repeatedly in a same capture device, as frame data for performing the time correction process; and restricting, by using the computer, a time difference of frame data used when the time correction process is performed.
    Type: Application
    Filed: July 8, 2013
    Publication date: November 7, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Koutarou CHIHARA, Harutaka TANAKA, Wataru NAKAMURA, TAKAO SHIKAMA
  • Publication number: 20130102115
    Abstract: The disclosed method for manufacturing an active matrix substrate includes a step in which a first mask is used to pattern a first conductive layer G, CS, and S, a step in which a second mask is used to pattern a first insulating layer, a step in which a third mask is used to pattern a semiconductor layer, a step in which a fourth mask is used to pattern a second conductive later, a step in which a fifth mask is used to pattern a second insulating layer, and a step in which a sixth mask is used to pattern a third conductive layer.
    Type: Application
    Filed: July 1, 2011
    Publication date: April 25, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Takeshi Yaneda, Hiromitsu Katsui, Wataru Nakamura
  • Patent number: 8421302
    Abstract: According to one embodiment, there is provided a rotating electrical machine including a core, a coil extending from the core, and an electromagnetic shield which is provided outside the core, and has a plurality of shoulders projecting toward the coil. The coil includes an insulator covering outside of a conductor, a resistance layer formed on a surface of the insulator and contacting the core, and at least one potential grading layer formed on a surface of the insulator adjacent to the resistance layer. A boundary between the resistance layer and potential grading layer is provided at a position farther from the core than a point on a surface of the coil, where a distance between the coil and a shoulder of the electromagnetic shield closest to the core is the shortest.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: April 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Harakawa, Tetsushi Okamoto, Yoshiyuki Inoue, Tooru Ootaka, Hiroshi Hatano, Mikio Kakiuchi, Toshihiko Shinoda, Makoto Kawahara, Masashi Kobayashi, Wataru Nakamura, Ken Nagakura, Masamitsu Sakuma
  • Patent number: 8405808
    Abstract: An active matrix substrate includes a substrate; scanning lines formed on the substrate; an insulating film covering the scanning lines; signal lines intersecting the scanning lines via the insulating film; switching elements formed on the substrate, each operating in response to a signal which is applied to the corresponding scanning line; and pixel electrodes each capable of being electrically connected to the corresponding signal line via the switching elements. The insulating film is a multilayer insulating film including a first insulating layer and a second insulating layer. The first insulating layer is formed of an insulating material containing an organic component, and the multilayer insulating film has a low-stack region in at least a portion of a region overlapping each switching element, the first insulating layer not being formed in the low-stack region.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: March 26, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Wataru Nakamura, Atsushi Ban, Shoji Okazaki, Hiromitsu Katsui, Yoshihiro Okada
  • Publication number: 20130048999
    Abstract: A semiconductor device (18) includes: a gate electrode (102) formed on a substrate (101); a semiconductor layer (104) formed above the gate electrode (102) and including a source region, a drain region, and a channel region; a source electrode (106) connected to the source region above the semiconductor layer (104); and a drain electrode (107) connected to the drain region above the semiconductor layer (104). The semiconductor layer (104) has, at a portion overlapping the drain electrode (107), a protrusion that protrudes outward along an extending direction of a drain line drawn out from the drain electrode (107). At an outside of the channel region sandwiched between the drain electrode (107) and the source electrode (106), the semiconductor layer (104) has an adjustment portion where an outer boundary of the semiconductor layer (104) is positioned more inward than an outer boundary of the gate electrode (102).
    Type: Application
    Filed: April 27, 2011
    Publication date: February 28, 2013
    Inventors: Shoji Okazaki, Takeshi Yaneda, Wataru Nakamura, Hiromitsu Katsui