Patents by Inventor Wataru Nakamura

Wataru Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130048904
    Abstract: The present invention provides an etching liquid for a multilayer thin film containing a copper layer and a titanium layer, and a method of using it for etching a multilayer thin film containing a copper layer and a titanium layer, that is, an etching liquid for a multilayer thin film containing a copper layer and a titanium layer, which comprises (A) hydrogen peroxide, (B) nitric acid, (C) a fluoride ion source, (D) an azole, (E) a quaternary ammonium hydroxide and (F) a hydrogen peroxide stabilizer and has a pH of from 1.5 to 2.5, and a etching method of using it.
    Type: Application
    Filed: January 28, 2011
    Publication date: February 28, 2013
    Applicants: SHARP KABUSHIKI KAISHA, MITSUBISHI GAS CHEMICAL COMPANY, INC.
    Inventors: Tomoyuki Adaniya, Satoshi Okabe, Toshiyuki Gotou, Taketo Maruyama, Kazuki Kobayashi, Keiichi Tanaka, Wataru Nakamura, Kenichi Kitoh, Tetsunori Tanaka
  • Publication number: 20130009160
    Abstract: Disposed on an insulating substrate (10a) are a plurality of TFTs arranged in a matrix, each including a drain electrode (18b) in which a first conductive layer (16b) and a second conductive layer (17bb) are laminated in this order; an interlayer insulating film (21) deposited on each of the TFTs, in which a plurality of contact holes (21a) reaching to the respective drain electrodes (18b) are formed; and a plurality of pixel electrodes (22a) disposed on the interlayer insulating film (21) in a matrix, each connected to a corresponding drain electrode (18b) via a corresponding contact hole (21a), being susceptible to an electric corrosion reaction with the second conductive layer (17bb). At a side of the drain electrode, which is connected to the pixel electrode (22a), a top surface of the first conductive layer (16b) is exposed from the second conductive layer (17bb). The interlayer insulating film (21) is disposed to cover the second conductive layer (17bb).
    Type: Application
    Filed: December 7, 2010
    Publication date: January 10, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Hiromitsu Katsui, Wataru Nakamura, Kenichi Kitoh
  • Patent number: 8305145
    Abstract: A receiving circuit in accordance with an exemplary aspect of the present invention includes a first voltage-dividing circuit that outputs a first input signal obtained by voltage division of one of differential signals based on the resistance ratio between first and second resistors, a second voltage-dividing circuit that outputs a second input signal obtained by voltage division of the other of the differential signals based on the resistance ratio between third and fourth resistors, a differential amplifier that amplifies the differential component between the first and second input signals, a common-mode voltage detection circuit that detects the common-mode voltage of the differential signals, and a bias voltage switching circuit that switches the voltage value of a bias voltage based on the common-mode voltage.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: November 6, 2012
    Assignee: RENESAS Electronics Corporation
    Inventor: Wataru Nakamura
  • Publication number: 20120248450
    Abstract: The present invention provides an active matrix substrate that is capable of reliably connecting a plurality of conductive layers that are arranged with an insulating layer therebetween. The active matrix substrate of the present invention has a first conductive layer (CS) and a second conductive layer (30), and an insulating layer (22) formed to cover the first conductive layer (CS) is provided. The first conductive layer (CS) has an end portion (CS1) formed to protrude within an opening portion (H1) formed in the insulating layer (22), and the second conductive layer (30) is provided to cover at least a part of the edge of the opening portion (H1) and to be connected directly to the end portion (CS1) of the first conductive layer (CS) within the opening portion (H1).
    Type: Application
    Filed: November 2, 2010
    Publication date: October 4, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Takeshi Yaneda, Hiromitsu Katsui, Wataru Nakamura
  • Publication number: 20120248443
    Abstract: An active matrix substrate includes a plurality of scanning lines (11a) extending parallel to each other; a plurality of signal lines (16a) extending parallel to each other in a direction crossing the scanning lines (11a); a plurality of TFTs (5) each provided at each of intersections of the scanning lines (11a) and the signal lines (16a), and each including a semiconductor layer (4a); and a coating type insulating layer formed between each of the scanning lines (11a) and each of the signal lines (16a). A plurality of openings (15a) are formed in the insulating layer such that each of the semiconductor layers (4a) is exposed, and at least part of a peripheral end of the opening (15a) of the insulating layer is positioned on an inner side relative to each of peripheral ends of the semiconductor layers (4a).
    Type: Application
    Filed: December 7, 2010
    Publication date: October 4, 2012
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Hiromitsu Katsui, Wataru Nakamura
  • Patent number: 8185056
    Abstract: In a load testing system, a transmission device measures a bandwidth of user data transmitted from a user terminal in real time, calculates a calculation bandwidth by subtracting the bandwidth of the user data from an evaluation bandwidth preset to evaluate the performance of a network, and transmits test data corresponding to the calculation bandwidth with the user data corresponding to the bandwidth of the user data. A reception device receives the user data and the test data transmitted with the user data, and evaluates the performance of the network based on the user data and test data.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: May 22, 2012
    Assignee: Fujitsu Limited
    Inventors: Shigeru Kotabe, Eitatsu Yoshida, Yoshihiko Koga, Wataru Nakamura, Wataru Nakashima
  • Publication number: 20120120616
    Abstract: A wiring board is provided which can prevent a metal electrode from corroding due to a defect in a transparent conductive electrode covering an end face of an organic insulating film. An active-matrix substrate includes: a glass substrate; a metal wire provided on the glass substrate; a gate insulating film covering the metal wire; an interlayer insulating film covering the gate insulating film; and a transparent electrode formed on the interlayer insulating film. The scanning wire provided with a terminal area where the transparent electrode is laminated directly on the scanning wire. The transparent electrode extends over the terminal area in such a way as to cover an end face of the interlayer insulating film that faces the terminal area and an end face of the gate insulating film that faces the terminal area.
    Type: Application
    Filed: May 18, 2010
    Publication date: May 17, 2012
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Hiromitsu Katsui, Kenichi Kitoh, Wataru Nakamura
  • Publication number: 20110279766
    Abstract: A connecting terminal has a configuration in which a plurality of parts of a first line (2) and respective corresponding plurality of parts of a second line (6) are connected to each other by a transparent conductive thin film (10). In a connecting terminal part, the plurality of parts of the first line (2) and the respective corresponding plurality of parts of the second line (6) are connected to each other in parallel. With the configuration, it is possible to greatly reduce a risk of disconnection. It is therefore possible to prevent disconnection from being caused by corrosion in the connecting terminal part of a display apparatus etc.
    Type: Application
    Filed: December 1, 2009
    Publication date: November 17, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kenichi Kitoh, Wataru Nakamura, Tetsunori Tanaka, Takeshi Hara, Yuya Nakano
  • Publication number: 20110227085
    Abstract: The present invention is a substrate for use in a display panel. According to the substrate, lines (102, 106, 107, and 113) provided in a display region on the substrate are made up of multiple layers whose uppermost layers (102c, 106c, 107c, and 113c) are each made from (i) an oxide of first metal selected from the group consisting of copper, titanium, and molybdenum or (ii) a nitride of copper. This can prevent external light from being reflected and thereby improve a contrast in a bright room.
    Type: Application
    Filed: November 5, 2009
    Publication date: September 22, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Wataru Nakamura, Kenichi Kitoh, Tetsunori Tanaka, Takeshi Hara, Yuya Nakano
  • Patent number: 8014297
    Abstract: According to an aspect of an embodiment, an apparatus is transmitting/receiving an OAM frame containing kinds of tests indicating one or more tests for Ethernet-OAM to/from a relay apparatus, storing configuration information to generate a network configuration needed for each of the plurality of tests in a pseudo manner, distinguishing the kind of test contained in the relevant OAM frame and obtaining network information of a network to which the relay apparatus that transmitted the OAM frame belongs and obtaining configuration information corresponding to the obtained network information obtained from the stored configuration information.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: September 6, 2011
    Assignee: Fujitsu Limited
    Inventors: Eitatsu Yoshida, Wataru Nakamura
  • Publication number: 20110169565
    Abstract: A receiving circuit in accordance with an exemplary aspect of the present invention includes a first voltage-dividing circuit that outputs a first input signal obtained by voltage division of one of differential signals based on the resistance ratio between first and second resistors, a second voltage-dividing circuit that outputs a second input signal obtained by voltage division of the other of the differential signals based on the resistance ratio between third and fourth resistors, a differential amplifier that amplifies the differential component between the first and second input signals, a common-mode voltage detection circuit that detects the common-mode voltage of the differential signals, and a bias voltage switching circuit that switches the voltage value of a bias voltage based on the common-mode voltage.
    Type: Application
    Filed: January 12, 2011
    Publication date: July 14, 2011
    Applicant: Renesas Electronics Corporation
    Inventor: Wataru Nakamura
  • Patent number: 7933210
    Abstract: According to an aspect of an embodiment, an apparatus is transmitting/receiving an OAM frame containing kinds of tests indicating one or more tests for Ethernet-OAM to/from a relay apparatus, storing configuration information to generate a network configuration needed for each of the plurality of tests in a pseudo manner, distinguishing the kind of test contained in the relevant OAM frame and obtaining network information of a network to which the relay apparatus that transmitted the OAM frame belongs and obtaining configuration information corresponding to the obtained network information obtained from the stored configuration information.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: April 26, 2011
    Assignee: Fujitsu Limited
    Inventors: Eitatsu Yoshida, Wataru Nakamura
  • Publication number: 20110074241
    Abstract: According to one embodiment, there is provided a rotating electrical machine including a core, a coil extending from the core, and an electromagnetic shield which is provided outside the core, and has a plurality of shoulders projecting toward the coil. The coil includes an insulator covering outside of a conductor, a resistance layer formed on a surface of the insulator and contacting the core, and at least one potential grading layer formed on a surface of the insulator adjacent to the resistance layer. A boundary between the resistance layer and potential grading layer is provided at a position farther from the core than a point on a surface of the coil, where a distance between the coil and a shoulder of the electromagnetic shield closest to the core is the shortest.
    Type: Application
    Filed: September 28, 2010
    Publication date: March 31, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi Harakawa, Tetsushi Okamoto, Yoshiyuki Inoue, Tooru Ootaka, Hiroshi Hatano, Mikio Kakiuchi, Toshihiko Shinoda, Makoto Kawahara, Masashi Kobayashi, Wataru Nakamura, Ken Nagakura, Masamitsu Sakuma
  • Publication number: 20110057192
    Abstract: An active matrix substrate includes a substrate; scanning lines formed on the substrate; an insulating film covering the scanning lines; signal lines intersecting the scanning lines via the insulating film; switching elements formed on the substrate, each operating in response to a signal which is applied to the corresponding scanning line; and pixel electrodes each capable of being electrically connected to the corresponding signal line via the switching elements. The insulating film is a multilayer insulating film including a first insulating layer and a second insulating layer. The first insulating layer is formed of an insulating material containing an organic component, and the multilayer insulating film has a low-stack region in at least a portion of a region overlapping each switching element, the first insulating layer not being formed in the low-stack region.
    Type: Application
    Filed: November 15, 2010
    Publication date: March 10, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Wataru NAKAMURA, Atsushi BAN, Shoji OKAZAKI, Hiromitsu KATSUI, Yoshihiro OKADA
  • Patent number: 7864281
    Abstract: An active matrix substrate includes a substrate; scanning lines formed on the substrate; an insulating film covering the scanning lines; signal lines intersecting the scanning lines via the insulating film; switching elements formed on the substrate, each operating in response to a signal which is applied to the corresponding scanning line; and pixel electrodes each capable of being electrically connected to the corresponding signal line via the switching elements. The insulating film is a multilayer insulating film including a first insulating layer and a second insulating layer. The first insulating layer is formed of an insulating material containing an organic component, and the multilayer insulating film has a low-stack region in at least a portion of a region overlapping each switching element, the first insulating layer not being formed in the low-stack region.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: January 4, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Wataru Nakamura, Atsushi Ban, Shoji Okazaki, Hiromitsu Katsui, Yoshihiro Okada
  • Publication number: 20100259715
    Abstract: An active matrix substrate (30) of the present invention includes a substrate, a gate line (50) formed on the substrate, and an interlayer insulating layer (90) for insulating a layer formed on the gate line (50) from the gate line (50). In a region of the substrate, the interlayer insulating layer (90) is not provided on an upper surface of the gate line (50), and therefore, the upper surface is exposed. On the other hand, the insulating layer (90) is provided on the substrate so as to have contact with at least an edge face of the gate line (50) which edge face is on an extension of a longitudinal direction of the gate line (50).
    Type: Application
    Filed: August 4, 2008
    Publication date: October 14, 2010
    Inventors: Tetsunori Tanaka, Atsushi Ban, Tohru Senoo, Wataru Nakamura, Yukimine Shimada
  • Patent number: 7690834
    Abstract: The present invention provides a mixer and a mixing method which enable stable supply of slurry at a high flow rate with foam being uniformly mixed therein, and which enable reduction in consumption of foam to be fed to the slurry. The mixer (10) has a housing (20), a rotary disc (32), a slurry outlet port (45), a slurry delivery conduit (46) and a hollow connector section (47). A foam feeding port (41) is disposed in a predetermined position of an annular wall or the hollow connector section. The foam feeding port feeds the foam to the slurry, immediately before the slurry enters the slurry outlet port, or feeds the foam to the slurry in the hollow connector section. The slurry and the foam mix with each other at the slurry outlet port or on its downstream side. The foam is not substantially subjected to agitation impact of the mixer and a quantity of loss of the foam is reduced.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: April 6, 2010
    Assignee: Yoshino Gypsum Co., Ltd
    Inventors: Wataru Nakamura, Yuichi Hirooka
  • Publication number: 20090143020
    Abstract: In a load testing system, a transmission device measures a bandwidth of user data transmitted from a user terminal in real time, calculates a calculation bandwidth by subtracting the bandwidth of the user data from an evaluation bandwidth preset to evaluate the performance of a network, and transmits test data corresponding to the calculation bandwidth with the user data corresponding to the bandwidth of the user data. A reception device receives the user data and the test data transmitted with the user data, and evaluates the performance of the network based on the user data and test data.
    Type: Application
    Filed: November 21, 2008
    Publication date: June 4, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Shigeru KOTABE, Eitatsu YOSHIDA, Yoshihiko KOGA, Wataru NAKAMURA, Wataru NAKASHIMA
  • Publication number: 20090075605
    Abstract: A network has communication apparatuses communicatively interconnected in compliance with a maintenance protocol. An LBM frame transmission unit transmits an LBM frame to the network. An MEP information acquisition unit identifies a communication apparatus having transmitted an LBR frame as an MEP when the LBR frame is received, and acquires MEP information from the LBR frame. An LTM frame transmission unit transmits an LTM frame to the MEP identified by the MEP information acquisition unit. An MIP information acquisition unit identifies a communication apparatus as an MIP from an LTR frame when the LTR frame is received as a response to the LTM frame, and acquires MIP information indicating information about the MIP. A topology information generation unit generates topology information representing a configuration of the network from the MEP information acquired by the MEP information acquisition unit and the MIP information acquired by the MIP information acquisition unit.
    Type: Application
    Filed: September 8, 2008
    Publication date: March 19, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Eitatsu YOSHIDA, Wataru Nakamura, Wataru Nakashima
  • Publication number: 20080315204
    Abstract: Improves the electric current driving capability of a thin film transistor without the yield being decreased due to a defective leak between a source electrode/drain electrode and a gate electrode or due to a decrease in an off-characteristic. A thin film transistor according to the present invention includes a gate electrode; an insulating film covering the gate electrode; a semiconductor layer provided on the insulating film; and a source electrode and a drain electrode provided on the insulating film and the semiconductor layer. The insulating film is a multiple layer insulating film including a first insulating layer and a second insulating layer provided on the first insulating layer. The multiple layer insulating film has a low stacking region excluding the first insulating layer and a high stacking region in which the first insulating layer and the second insulating layer are stacked. The first insulating layer is provided so as to cover at least an edge of the gate electrode.
    Type: Application
    Filed: January 23, 2007
    Publication date: December 25, 2008
    Inventors: Yoshihiro Okada, Wataru Nakamura, Atsushi Ban