Abstract: A light emitting chip and associated package structure are provided. The light emitting chip includes a substrate, a first type layer, an active layer, a second type layer, a first type electrode and a second type electrode. A second portion of the first type layer is located over the substrate. A first portion of the first type layer is located over the second portion of the first type layer. The active layer is located over the first portion of the first type layer. The second type layer is located over the active layer. The first type electrode is contacted with a sidewall of the second portion of the first type layer and contacted with a sidewall of the substrate. The second type electrode is contacted with the second type layer.

Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die is disposed on and electrically coupled to the first surface of the first RDL structure. A first molding compound is disposed on the first surface of the first RDL structure and surrounds the first semiconductor die. A plurality of solder balls or conductive pillar structures is disposed in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure. A method for forming the semiconductor package is also provided.

Abstract: A method of fabricating a memory device includes firming an oxide layer on a semiconductor substrate, and forming an isolation structure in the semiconductor substrate and the oxide layer to define an active area. The method also includes forming a word line and a bit line in the semiconductor substrate, wherein the bit line is above the word line. The method further includes removing the oxide layer to form a recess between the isolation structure and the bit line, and forming a storage node contact in the recess. In addition, from a top view, the storage node contact of the memory device overlaps a corresponding portion of the active area.

Abstract: A textile with conductive structures includes a fabric substrate, an outer conductive structure made of polymer and disposed on the fabric substrate, and an inner conductive structure disposed under the outer conductive structure and electrically connected to the outer conductive structure. The sheet resistance of the inner conductive structure is lower than the sheet resistance of the outer conductive structure. The total sheet resistance of the inner and outer conductive structures is less than 100 ohms per square when the textile undergoes a laundery procedure.

Abstract: A display device includes: a plurality of first signal lines, a plurality of second signal lines, and a plurality of sensing pads. The first signal lines are disposed in a first direction, and are parallel to each other. The second signal lines are disposed in a second direction, and are parallel to each other. The second signal lines are substantially perpendicular to the first signal lines. A first row and a second row of the sensing pads are disposed in zigzag in the second direction.

Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.

Abstract: A heat sink is applied to a display unit and has a heat conductor, at least one first cooling fan, and at least one second cooling fan. The heat conductor has a heat-conducting member, multiple first cooling fins, and multiple second cooling fins. The heat-conducting member has a base portion, an extending portion formed on the base portion, and multiple channels formed in the heat-conducting member and filled with a working fluid. The first cooling fins are formed on the base portion. The second cooling fins are formed on the extending portion. The at least one first cooling fan is disposed on the base portion. The at least one second cooling fan is disposed on the extending portion. The heat conductor can be sectioned and the working fluid can change phases for heat dissipation, providing a good heat dissipation effect to the heat sink is good.

Abstract: A heat dissipating apparatus has a phase change material evaporator, a condenser, a refrigerant output tube, and a refrigerant input tube. The evaporator has a base having an evaporation chamber, a refrigerant inlet and a refrigerant outlet, a reinforcement panel mounted in the evaporation chamber and dividing the evaporation chamber into two spaces, and multiple heat conduction fins separately arranged in the two spaces. An opening area of the refrigerant outlet is larger than an opening area of the refrigerant inlet. The evaporator, the refrigerant output tube, the condenser and the refrigerant input tube form a closed refrigerant circulation loop with a refrigerant filled therein. Gas pressure of a gas-phased refrigerant in the two spaces can be increased. With pressure difference between the refrigerant outlet and the refrigerant inlet, the gas-phased refrigerant can be accelerated to flow toward the refrigerant outlet and flowability of the refrigerant can be increased.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes.

Abstract: A memory device includes a semiconductor substrate having at least one active area that is defined by a device isolation structure. The memory device further includes two neighboring buried word lines disposed in the semiconductor substrate of the active area. The memory device further includes a trench isolation structure disposed in the semiconductor substrate between the buried word lines.

Abstract: A method for fabricating a semiconductor substrate is disclosed, which includes: forming a first dielectric layer on a substrate body; foil ling a plurality of first vias penetrating the first dielectric layer to expose portions of the substrate body; forming a second dielectric layer on the first dielectric layer and the exposed portions of the substrate body, wherein the second dielectric layer extends on walls of the first vias; etching the second dielectric layer to form a plurality of openings communicating with the first vias and form a plurality of second vias penetrating the second dielectric layer in the first vias so as to expose portions of the substrate body, leaving the second dielectric layer on the walls of the first vias; and forming a circuit layer in the openings, and forming a plurality of conductive vias in the second vias for electrically connecting the circuit layer and the substrate body.

Abstract: An electrical connection structure is provided in the present invention, which includes a substrate, a plurality of conductive textile layers disposed apart on the substrate, an electrical connection layer disposed on the conductive textile layers, a plurality conductive parts disposed on the electrical connection layer corresponding to the conductive textile layers respectively, an adhesive layer, and a protective layer, wherein the electrical connection layer provides the electrical connection between the conductive textile layers and the conductive parts corresponding to the conductive textile layers, and the conductive textile layers disposed apart from each other are not electrically connected.

Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die and a first molding compound that surrounds the first semiconductor die are disposed on the first surface of the first RDL structure. An IMD structure having a conductive layer with an antenna pattern or a conductive shielding layer is disposed on the first molding compound and the first semiconductor die.

Abstract: A semiconductor structure includes a substrate, and first isolation structures, at least one buried word line and at least one second isolation structure which are disposed in the substrate. The buried word line intersects the first isolation structures. The second isolation structure intersects the first isolation structures. A material of at least a portion of the second isolation structure is different from a material of the first isolation structures.

Abstract: A textile with conductive structures includes a fabric substrate, an outer conductive structure made of polymer and disposed on the fabric substrate, and an inner conductive structure disposed under the outer conductive structure and electrically connected to the outer conductive structure. The sheet resistance of the inner conductive structure is lower than the sheet resistance of the outer conductive structure. The total sheet resistance of the inner and outer conductive structures is less than 100 ohms per square when the textile undergoes a laundery procedure.

Abstract: An electrical connection structure is provided in the present invention, which includes a substrate, a plurality of conductive textile layers disposed apart on the substrate, an electrical connection layer disposed on the conductive textile layers, a plurality conductive parts disposed on the electrical connection layer corresponding to the conductive textile layers respectively, an adhesive layer, and a protective layer, wherein the electrical connection layer provides the electrical connection between the conductive textile layers and the conductive parts corresponding to the conductive textile layers, and the conductive textile layers disposed apart from each other are not electrically connected.

Abstract: This application discloses a physical unclonable function device including physical unclonable function units, each capable of generating an output. The physical unclonable function device can utilize transforms to derive bits from the outputs and utilize the derived bits to generate an identifier for the physical unclonable function device. An inspection configuration tool can sample multiple outputs from each of the physical unclonable function units, identify a transforms to perform on a future output for each of the physical unclonable function units based on a distribution of values corresponding to the sampled outputs. The inspection configuration tool can configure the physical unclonable function device to perform the transforms on the future outputs of the physical unclonable function units. Embodiments will be described below in greater detail.

Abstract: A liquid heat-dissipating assembly has a heat-guiding tube assembly, multiple heat-dissipating units, and at least one heat-dissipating tube. The heat-guiding tube assembly has a first tube, a second tube, and a separating segment. The first tube has at least one first channel. The second tube has at least one second channel. The separating segment is mounted between the first tube and the second tube. The heat-dissipating units are connected with the heat-guiding tube assembly, and each heat-dissipating unit has a heat-dissipating body, a first pipe, and a second pipe. The heat-dissipating body has a passage. The first pipe is connected with the passage and the at least one first channel. The second pipe is connected with the passage and the at least one second channel. The at least one heat-dissipating tube is connected with the at least one second channel of the second tube.

Abstract: Provided is a bipolar electrode probe, which includes a conductive needle, an insulation layer, a conductive sleeve, and an insulation sleeve. The conductive needle has a longitudinal direction and a transverse direction perpendicular to the longitudinal direction. The insulation layer covers the conductive needle and has a first opening. The conductive sleeve covers the insulation layer and has a second opening. The insulation sleeve covers the conductive sleeve. When the bipolar electrode probe is turned on, a longitudinal electric field is formed from a front end of the conductive needle to the conductive sleeve along the longitudinal direction. A transverse electric field is formed from the conductive needle to the conductive sleeve via the first opening and the second opening along the transverse direction.

Abstract: Provided is a memory device including a substrate, isolation structures, conductive pillars, and bit-line structures. The substrate includes active areas. The active areas are arranged as a first array. The isolation structures are located in the substrate and extending along a Y direction. Each of the isolation structures is arranged between the active areas in adjacent two columns. The conductive pillars are located on the substrate and arranged as a second array. The conductive pillars in adjacent two rows are in contact with the active areas arranged as the same column, to form a first contact region and a second contact region. The bit-line structures are arranged on the substrate in parallel along a X direction. Each of the bit-line structures is in contact with the active areas arranged as the same column, to form a third contact region between the first and second regions.