Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and a plurality of first conductive layers; a first passivation layer overlying the plurality of IMD layers and the first conductive layers; at least a first power/ground mesh wiring line in a first aluminum layer overlying the first Insulating layer; and at least a second power/ground mesh wiring line in a second aluminum layer overlying the first aluminum layer.

Abstract: An air duct defines a first air vent and a second air vent at opposite ends thereof, respectively. The air duct includes a duct body and a movable plate. The duct body defines a through opening in a side thereof. The through hole intercommunicates an interior and an exterior of the air duct. The movable plate is mounted on the side of the duct body adjacent to the through opening. By moving the movable plate, the through opening can be changed between an open state and a closed state freely. An electronic device incorporating the air duct is also provided.

Abstract: A transforming circuit includes: a first winding having a first port and a second port operably coupled for a differential signal; and a plurality of second windings, each having a third port and a fourth port operably coupled for a single-ended signal when magnetically coupled to the first winding. When one of the second windings is magnetically coupled to the first winding, each remaining second winding(s) is not magnetically coupled to the first winding.

Abstract: A phase locked loop (PLL) with a loop bandwidth calibration circuit is provided. The mixed-mode PLL comprises an analog phase correction path, a digital frequency correction path, a calibration current source, and a loop bandwidth calibration circuit. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. The calibration current source is coupled to the LPCU. The loop bandwidth calibration circuit is coupled to a frequency divider and coupled between the input and output of the PLL. The loop bandwidth calibration circuit operates after the calibration current source injects a calibration current into the LPCU.

Abstract: Disclosed herein is a chromate-free conversion film solution and a method of applying the solution to magnesium and magnesium alloys. The solution contains zirconium ions, manganese ions, barium ions and phosphate corrosion inhibitor; and the pH of the said solution is in the range of 1-5; and may further comprise molybdate as accelerant. The method comprises degreasing, acid etching, surface activation, surface adjusting, and film forming steps. The conversion film obtained in accordance with the disclosed method is uniform, smooth, and compact and has high corrosion resistance and good adhesion with paint film. Moreover, the chromate-free conversion film solution is environmentally friendly and possesses fast film growth rates.

Abstract: A signal generating apparatus includes: a test data generator for generating a test data; a fractional-N phase-locked loop device coupled to the test data generator for generating a synthesized signal according to the test data when the test data is received; and a calibrating device coupled to the fractional-N phase-locked loop device for measuring power of the synthesized signal to generate a calibration signal utilized for adjusting the fractional-N phase-locked loop device.

Abstract: An exemplary of an anti-vibration hard disk drive assembly includes a hard disk drive, a bracket containing the hard disk drive, a rack supporting the hard disk drive and the bracket, and an elastic structure disposed between the bracket and the rack. The rack includes a pair of rails supporting the bracket thereon. The elastic structure is disposed between the bracket and the pair of rails of the rack, whereby a vibration caused operation of the hard disk drive can be absorbed by the elastic structure.

Abstract: A fixing apparatus for securing an HDD, includes a carrier containing the HDD and a plurality of fixtures to secure the HDD in the carrier. The carrier includes a bottom frame and two opposite sidewalls connected to two opposite edges of the bottom frame. Each fixture includes a post and a cushion. The cushions are fixed in the sidewalls and abut against two opposite sides of the HDD. The posts are extended through the cushions and inserted into the two opposite sides of the HDD to hold the HDD spaced apart from the bottom frame and the sidewalls of the carrier.

Abstract: The present invention provides a highly specific anti-Caveolin-1 polyclonal antibody, which is prepared by the following steps: (1) providing an antigen comprising a fragment of Caveolin-1 peptide sequence SEQ ID NO: 1; and (2) subcutaneously injecting said antigen into a rabbit to produce the anti-Caveolin-1 polyclonal antibody. The present invention also provides an antigen and a method used for preparing the anti-Caveolin-1 polyclonal antibody, and a kit used for detecting Caveolin-1 in a specimen.

Abstract: An image de-interlacing method for estimating an interpolation luminance of an interpolated pixel, including: selecting a plurality of first and second candidate pixels respectively on upper and lower lines adjacent to the interpolated pixel, calculating a plurality of weighted directional differences respectively associated with one of the first candidate pixels and one of the second candidate pixels with weighting values determined by comparing similarity of luminance decreasing/increasing patterns near the associated first and second candidate pixels on the upper and lower lines, selecting a first selected pixel and a second selected pixel respectively from the first and second candidate pixels associated with the smallest weighted directional difference, and obtaining the interpolation luminance according to the first and second selected pixels.

Abstract: A phase locked loop (PLL) with a loop bandwidth calibration circuit is provided. The mixed-mode PLL comprises an analog phase correction path, a digital frequency correction path, a calibration current source, and a loop bandwidth calibration circuit. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. The calibration current source is coupled to the LPCU. The loop bandwidth calibration circuit is coupled to a frequency divider and coupled between the input and output of the PLL. The loop bandwidth calibration circuit operates after the calibration current source injects a calibration current into the LPCU.

Abstract: A temperature compensated oscillation circuit capable of providing a stable frequency output over temperature is provided, in which an oscillator with a crystal resonator is arranged to generate an oscillation signal with an output frequency, and a temperature sensor provides a temperature compensation voltage of which a function is linear with respect to an ambient temperature of the oscillator. A first accumulation mode MOS varactor is coupled to the oscillator, and the first accumulation mode MOS varactor adjusts a capacitance thereof in response to the temperature compensation voltage, such that the coupled oscillator has a frequency compensation over temperature for the oscillation signal, wherein the frequency compensation substantially varies as an inverse function of a deviation of the crystal resonator over temperature when the ambient temperature is within a predetermined temperature range.

Abstract: A phase locked loop frequency synthesizer including a phase locked loop, a frequency regenerator and a modulation processor, resistant to distortion induced by the frequency regenerator and conforming to transmission specifications. The phase locked loop comprises a detector generating a phase detection signal based on phase difference between a reference signal and a feedback signal, a loop filter, a voltage control oscillator generating a first output modulation signal and a frequency dividing unit varying a division factor based on a processed input modulation signal and dividing the frequency of the first output modulation signal by a division factor to generate the feedback signal. The frequency regenerator generates a second output modulation signal with a frequency range not overlapping an output frequency range of the voltage control oscillator.

Abstract: A phase locked loop (PLL) directly uses a charge pump and loop filter therein for fast and low-costly calibration. The PLL comprises a charge pump, a loop filter, a voltage comparator, a counting device, and a calibration device. The loop filter comprises a voltage storage device coupled to the charge pump for charging by the charge pump, wherein the voltage storage device comprises a variable impedance. The voltage comparator is coupled to a voltage reference and to the voltage storage device for comparing a voltage of the storage device and a voltage of the voltage reference. The counting device is coupled to the voltage comparator to measure the charge time required for the voltage of the voltage storage device to substantially equal to the voltage of the voltage reference. The calibration device adjusts the variable impedance to adjust the time measured by the counting device to a desired time.

Abstract: A dynamic carrying method to prevent saturation of a sigma-delta modulator of a phase locked loop frequency synthesizer. The phase locked loop frequency synthesizer using the dynamic carrying method comprises a forward portion receiving a reference frequency signal and a first frequency signal to generate an output carrier signal; a multi-modulus divider dividing the output carrier signal frequency to generate the first frequency signal; a dynamic carrying device receiving and separating transmitting data into a carrying part and a residue part when the transmitting data amplitude exceeds a threshold; a sigma-delta modulator receiving the residue part to generate a first modulus control signal; an auxiliary modulator receiving the carrying part to generate a second modulus control signal; and a first adder receiving the first modulus control signal, the second modulus control signal, and a third modulus control signal and outputting a modulus modulation signal to modulate the multi-modulus divider.

Abstract: The present invention provides a highly specific anti-Caveolin-1 polyclonal antibody, which is prepared by the following steps: (1) providing an antigen comprising a fragment of Caveolin-1 peptide sequence SEQ ID NO: 1; and (2) subcutaneously injecting said antigen into a rabbit to produce the anti-Caveolin-1 polyclonal antibody. The present invention also provides an antigen and a method used for preparing the anti-Caveolin-1 polyclonal antibody, and a kit used for detecting Caveolin-1 in a specimen.

Abstract: A signal generating apparatus is disclosed. The signal generating apparatus includes a test data generator for generating a test data; a fractional-N phase-locked loop device coupled to the test data generator for generating a synthesized signal according to the test data when the test data is received; and a calibrating device coupled to the fractional-N phase-locked loop device for measuring power of the synthesized signal to generate a calibration signal utilized for adjusting the fractional-N phase-locked loop device.

Abstract: A signal generating apparatus is disclosed. The signal generating apparatus includes a phase-locked loop device for generating a synthesized signal, wherein the phase-locked loop device includes a phase detector, a charge pump device, a filtering device, a controllable oscillator, and a switch device coupled to the controllable oscillator for selectively coupling the controllable oscillator to the filtering device or a tuning reference signal; a calibration controller generates a tuning reference signal and controls the switch device; and a first calibrator tunes the controllable oscillator into a predetermined sub-band according to a reference oscillating signal and a synthesized signal when the switch device couples the controllable oscillator to the tuning reference signal of the calibration controller.

Abstract: A signal generating apparatus is disclosed for generating a synthesized signal according to an input signal. The signal generating apparatus includes a phase-locked loop device for generating the synthesized signal; a detecting device for detecting a reference signal to generate a calibrating signal; a filtering device for filtering the input signal and calibrating the input signal according to the calibrating signal to generate a filtered input signal; and a modulating device for modulating the filtered input signal in the normal operation mode and setting the dividing factor according to a first factor setting or a second factor setting in the calibration mode.