Patents by Inventor Wei Ke
Wei Ke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080272811Abstract: A signal generating apparatus is disclosed for generating a synthesized signal according to an input signal. The signal generating apparatus includes a phase-locked loop device for generating the synthesized signal; a detecting device for detecting a reference signal to generate a calibrating signal; a filtering device for filtering the input signal and calibrating the input signal according to the calibrating signal to generate a filtered input signal; and a modulating device for modulating the filtered input signal in the normal operation mode and setting the dividing factor according to a first factor setting or a second factor setting in the calibration mode.Type: ApplicationFiled: March 23, 2007Publication date: November 6, 2008Inventors: Hsin-Hung Chen, Tai-Yuan Yu, Ling-Wei Ke, Tser-Yu Lin
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Publication number: 20080272851Abstract: A tunable capacitance unit coupled between a pair of circuit nodes. The tunable capacitance unit comprises a tuning input supplying a tuning voltage, and first and second tuning capacitance units. Each of the tuning capacitance units comprises a pair of accumulation-mode MOS varactors with source/drains thereof coupled to the tuning input, a pair of blocking capacitors coupled to a respective gate of the accumulation-mode MOS varactors and to a respective one of the circuit nodes, and a pair of biasing resistors coupled to a respective gate of the accumulation-mode MOS varactors and to a respective bias terminal receiving a respective reference voltage. The reference voltages received by the first and second tuning capacitance units are symmetrical to a predetermined voltage.Type: ApplicationFiled: May 4, 2007Publication date: November 6, 2008Inventors: Tser-Yu Lin, Ling-Wei Ke, Tai-Yuan Yu
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Publication number: 20080232443Abstract: A signal generating apparatus for generating a synthesized signal according to an input signal is provided. The signal generating apparatus includes a phase-locked loop device and a control unit. The phase-locked loop device has a phase/frequency detector for generating a detected signal according to a reference oscillating signal and a feedback signal, a control signal generator for generating a control signal according to the detected signal, a voltage controlled oscillator for generating the synthesized signal according to the control signal, and a divider for dividing the synthesized signal according to a dividing factor to generate the feedback signal. The control unit is for controlling the control signal generator to adjust the control signal in a calibration mode to thereby adjust a frequency of the synthesized signal. The phase/frequency detector does not output the detected signal to the control signal generator in the calibration mode.Type: ApplicationFiled: April 23, 2008Publication date: September 25, 2008Inventors: Tai-Yuan Yu, Ping-Ying Wang, Ling-Wei Ke, Hsin-Hung Chen
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Patent number: 7397227Abstract: A low-noise voltage regulator circuit with quick disablement includes an amplifier for outputting a driving voltage according to a reference voltage, a feedback voltage on a feedback node, and an enable signal; an output transistor coupled among the amplifier, an output node, and a first voltage source for outputting an output voltage at the output node; a first discharge transistor having a first size and coupled among the enable signal, the output node, and the feedback node; and a second discharge transistor having a second size being different than the first size and coupled among the enable signal, the feedback node, and a second voltage source; wherein when the enable signal disables the amplifier, the enable signal turns on the first discharge transistor and the second discharge transistor such that the output voltage is quickly pulled down to close a level provided by the second voltage source.Type: GrantFiled: May 17, 2006Date of Patent: July 8, 2008Assignee: MediaTek Inc.Inventors: Ling-Wei Ke, Chi-Kun Chiu
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Publication number: 20080157823Abstract: A dynamic carrying method to prevent saturation of a sigma-delta modulator of a phase locked loop frequency synthesizer. The phase locked loop frequency synthesizer using the dynamic carrying method comprises a forward portion receiving a reference frequency signal and a first frequency signal to generate an output carrier signal; a multi-modulus divider dividing the output carrier signal frequency to generate the first frequency signal; a dynamic carrying device receiving and separating transmitting data into a carrying part and a residue part when the transmitting data amplitude exceeds a threshold; a sigma-delta modulator receiving the residue part to generate a first modulus control signal; an auxiliary modulator receiving the carrying part to generate a second modulus control signal; and a first adder receiving the first modulus control signal, the second modulus control signal, and a third modulus control signal and outputting a modulus modulation signal to modulate the multi-modulus divider.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Applicant: MEDIATEK INC.Inventors: Tai Yuan Yu, Ling-Wei Ke, Tser-Yu Lin, Hsin-Hung Chen
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Patent number: 7382201Abstract: A signal generating apparatus is disclosed for generating a synthesized signal according to an input signal, the signal generating apparatus includes a phase-locked loop device for generating the synthesized signal; a control unit for controlling the control signal generator to adjust the control signal in a calibration mode to thereby adjust a frequency of the synthesized signal, wherein the phase/frequency detector does not output the detected signal to the control signal generator in the calibration mode; a detecting device for detecting the synthesized signal to generate a calibrating signal in the calibration mode; a filtering device for filtering the input signal and calibrating the input signal according to the calibrating signal to generate a filtered signal; and a modulating device for modulating the filtered signal to generate the dividing factor.Type: GrantFiled: March 23, 2007Date of Patent: June 3, 2008Assignee: Mediatek Inc.Inventors: Tai-Yuan Yu, Ping-Ying Wang, Ling-Wei Ke, Hsin-Hung Chen
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Publication number: 20080111915Abstract: An image de-interlacing method for estimating an interpolation luminance of an interpolated pixel, including: selecting a plurality of first and second candidate pixels respectively on upper and lower lines adjacent to the interpolated pixel, calculating a plurality of weighted directional differences respectively associated with one of the first candidate pixels and one of the second candidate pixels with weighting values determined by comparing similarity of luminance decreasing/increasing patterns near the associated first and second candidate pixels on the upper and lower lines, selecting a first selected pixel and a second selected pixel respectively from the first and second candidate pixels associated with the smallest weighted directional difference, and obtaining the interpolation luminance according to the first and second selected pixels.Type: ApplicationFiled: November 15, 2006Publication date: May 15, 2008Applicant: FARADAY TECHNOLOGY CORP.Inventors: Yu-Chang Wang, Chih-Wei Ke, Kuo-Han Hsu
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Patent number: 7363013Abstract: A phase lock loop receives a baseband signal which has an input frequency, and modulating the baseband signal to be a corresponding RF signal which has a predetermined transmission frequency for transmitting. The phase lock loop comprises a programmable divider, a modulator, a phase detector, a charging pump, a loop filter, a voltage-controlled oscillator and a frequency converter. The programmable divider divides the frequency of a local oscillating signal by a programmable divisor to generate a reference signal. The modulator receives the baseband signal, modulates the frequency of the reference signal according to the baseband signal, and generates a corresponding first comparison signal. The frequency converter receives the feedback RF signal and the local oscillating signal and outputs the second comparison signal according to the frequency difference. The divisor of the divider is programmable to avoid the spur frequency being generated because the local oscillating signal is interfered.Type: GrantFiled: October 28, 2003Date of Patent: April 22, 2008Assignee: MediaTek Inc.Inventors: Chang-Fu Kuo, Ling-Wei Ke, Jen-Chiou Bo, Shou-Tsung Wang, Kuang-Kai Teng
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Publication number: 20080011230Abstract: Chemical vapor deposition equipment includes a reactor, an adjustable pipe, and an exhausted pipe. The adjustable pipe includes a compressible body, a bushing, and a ring positioned at an end of the body for connecting with the exhausted pipe. The bushing is positioned inside the body, and an end of the bushing is connected to the reactor for preventing exhaust gas from remaining inside the body. In addition, the compressible body is monolithically formed. Therefore, exhaust gas will not leak from the body, which improves the quality of manufacture.Type: ApplicationFiled: May 11, 2006Publication date: January 17, 2008Inventors: Chih-Wei Ke, Jen-Chi Chuang, Shih-Heng Fan
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Publication number: 20080003953Abstract: A phase locked loop frequency synthesizer including a phase locked loop, a frequency regenerator and a modulation processor, resistant to distortion induced by the frequency regenerator and conforming to transmission specifications. The phase locked loop comprises a detector generating a phase detection signal based on phase difference between a reference signal and a feedback signal, a loop filter, a voltage control oscillator generating a first output modulation signal and a frequency dividing unit varying a division factor based on a processed input modulation signal and dividing the frequency of the first output modulation signal by a division factor to generate the feedback signal. The frequency regenerator generates a second output modulation signal with a frequency range not overlapping an output frequency range of the voltage control oscillator.Type: ApplicationFiled: May 8, 2007Publication date: January 3, 2008Applicant: MEDIATEK INC.Inventors: Ling-Wei Ke, Tai Yuan Yu, Hsin-Hung Chen
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Patent number: 7298810Abstract: A programmable frequency divider for dividing the frequency of a source signal according to a selectable divisor which is obtained based on a plurality of divisor signals and outputting a result signal having a divided frequency includes at least one cell of a first type. The cells of the first type are cascaded with each other. The programmable frequency divider synchronously resets all of the cells of the first type according to a reset signal in order to selectively switch each cell of the first type to perform a divide-by-two or divide-by-three operation according to a corresponding divisor signal. The last cell of the first type outputs the result signal having the divided frequency.Type: GrantFiled: September 16, 2004Date of Patent: November 20, 2007Assignee: Mediatek IncorporationInventor: Ling-Wei Ke
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Publication number: 20060214651Abstract: A low-noise voltage regulator circuit with quick disablement includes an amplifier for outputting a driving voltage according to a reference voltage, a feedback voltage on a feedback node, and an enable signal; an output transistor coupled among the amplifier, an output node, and a first voltage source for outputting an output voltage at the output node; a first discharge transistor having a first size and coupled among the enable signal, the output node, and the feedback node; and a second discharge transistor having a second size being different than the first size and coupled among the enable signal, the feedback node, and a second voltage source; wherein when the enable signal disables the amplifier, the enable signal turns on the first discharge transistor and the second discharge transistor such that the output voltage is quickly pulled down to close a level provided by the second voltage source.Type: ApplicationFiled: May 17, 2006Publication date: September 28, 2006Inventors: Ling-Wei Ke, Chi-Kun Chiu
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Patent number: 7109690Abstract: A low-noise voltage regulator circuit with quick disablement is disclosed. The voltage regulator circuit includes an amplifier for outputting a driving voltage according to a reference voltage, a feedback voltage on a feedback node, and an enable signal; an output transistor coupled among the amplifier, an output node, and a first voltage source for outputting an output voltage at the output node; a first discharge transistor coupled among the enable signal, the output node, and the feedback node; and a second discharge transistor coupled among the enable signal, the feedback node, and a second voltage source; wherein when the enable signal disables the amplifier, the enable signal turns on the first discharge transistor and the second discharge transistor such that the output voltage is quickly pulled down to close a level provided by the second voltage source.Type: GrantFiled: September 29, 2004Date of Patent: September 19, 2006Assignee: Mediatek IncorporationInventors: Ling-Wei Ke, Chi-Kun Chiu
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Patent number: 7015742Abstract: A differential switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of eliminating clock feedthrough and preventing an unwanted momentary frequency shift and drift in the VCO output frequency when the switched capacitor circuit is shut off. A center switch element connects a positive side capacitance node with a negative side capacitance node depending on a first control signal. A positive side primary switch element and a negative side primary switch element connect the positive and negative side capacitance nodes depending on the first control signal. A positive side additional switch element and negative side additional switch element with control signals complementary to the first control signal cancel the clock feedthrough of the center switch and the positive and negative side primary switch elements at the positive and negative side capacitance nodes respectively.Type: GrantFiled: June 20, 2003Date of Patent: March 21, 2006Assignee: Media Tek Inc.Inventor: Ling-Wei Ke
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Publication number: 20050073286Abstract: A low-noise voltage regulator circuit with quick disablement is disclosed. The voltage regulator circuit includes an amplifier for outputting a driving voltage according to a reference voltage, a feedback voltage on a feedback node, and an enable signal; an output transistor coupled among the amplifier, an output node, and a first voltage source for outputting an output voltage at the output node; a first discharge transistor coupled among the enable signal, the output node, and the feedback node; and a second discharge transistor coupled among the enable signal, the feedback node, and a second voltage source; wherein when the enable signal disables the amplifier, the enable signal turns on the first discharge transistor and the second discharge transistor such that the output voltage is quickly pulled down to close a level provided by the second voltage source.Type: ApplicationFiled: September 29, 2004Publication date: April 7, 2005Inventors: Ling-Wei Ke, Chi-Kun Chiu
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Publication number: 20050058236Abstract: A programmable frequency divider for dividing the frequency of a source signal according to a selectable divisor which is obtained based on a plurality of divisor signals and outputting a result signal having a divided frequency includes at least one cell of a first type. The cells of the first type are cascaded with each other. The programmable frequency divider synchronously resets all of the cells of the first type according to a reset signal in order to selectively switch each cell of the first type to perform a divide-by-two or divide-by-three operation according to a corresponding divisor signal. The last cell of the first type outputs the result signal having the divided frequency.Type: ApplicationFiled: September 16, 2004Publication date: March 17, 2005Inventor: Ling-Wei Ke
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Patent number: 6847233Abstract: An emitter coupled logic circuit with a data reload function is disclosed. The emitter coupled logic (ECL) circuit includes first and second in series transistors consisting of bipolar junction transistors (BJTs) and field effect transistors (FETs), respectively. The bipolar junction transistor receives a reload signal, and the field effect transistor receives a reload data. Therefore, using the serial control of the bipolar junction transistors together with the field effect transistors, the digital reload data may be reloaded into the ECL circuit. Since the invention utilizes the field effect transistors to directly receive and set the reload data, it is not necessary to pre-convert the digital reload data into a front-stage ECL voltage level. In addition, because the reload data can be sent to the field effect transistors before the reload signal enables, the field effect transistors may be set to ON or OFF in advance.Type: GrantFiled: June 25, 2003Date of Patent: January 25, 2005Assignee: MediaTek Inc.Inventor: Ling-Wei Ke
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Publication number: 20040257143Abstract: A differential switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of eliminating clock feedthrough and preventing an unwanted momentary frequency shift and drift in the VCO output frequency when the switched capacitor circuit is shut off. A center switch element connects a positive side capacitance node with a negative side capacitance node depending on a first control signal. A positive side primary switch element and a negative side primary switch element connect the positive and negative side capacitance nodes depending on the first control signal. A positive side additional switch element and negative side additional switch element with control signals complementary to the first control signal cancel the clock feedthrough of the center switch and the positive and negative side primary switch elements at the positive and negative side capacitance nodes respectively.Type: ApplicationFiled: June 20, 2003Publication date: December 23, 2004Inventor: Ling-Wei Ke
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Publication number: 20040246040Abstract: A switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of minimizing clock feedthrough effect and an undesired momentary frequency drift in the VCO output frequency when the switched capacitor circuit is shut off. By gradually switching the switched capacitor circuit from an on state to an off state the clock feedthrough effect can be minimized. Several differently sized switch elements are used to selectively switch the capacitor from an internal capacitive node to ground. When switching the switched capacitor circuit to an off state, the control signals are sequenced to shut the switch elements off in order based on decreasing switch size. The smallest switch element can have a low-pass filter added to its control terminal to further decrease the clock feedthrough effect.Type: ApplicationFiled: May 6, 2004Publication date: December 9, 2004Inventors: Chi-Ming Hsiao, Guang-Kaai Dehng, Ming-Horng Tsai, Ling-Wei Ke, En-Hsiang Yeh, Chi-Kun Chiu
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Publication number: 20040246039Abstract: A switched capacitor circuit for use in a voltage controlled oscillator (VCO) capable of minimizing clock feedthrough effect and an undesired momentary frequency drift in the VCO output frequency when the switched capacitor circuit is shut off. By gradually switching the switched capacitor circuit from an on state to an off state the clock feedthrough effect can be minimized. Several differently sized switch elements are used to selectively switch the capacitor from an internal capacitive node to ground. When switching the switched capacitor circuit to an off state, the control signals are sequenced to shut the switch elements off in order based on decreasing switch size. The smallest switch element can have a low-pass filter added to its control terminal to further decrease the clock feedthrough effect.Type: ApplicationFiled: June 3, 2003Publication date: December 9, 2004Inventors: Chi-Ming Hsiao, Guang-Kaai Dehng, Ming-Horng Tsai, Ling-Wei Ke, En-Hsiang Yeh, Chi-Kun Chiu