Abstract: A pixel array including a pixel electrode and an active device is provided. The active device includes a gate, a channel layer, a source, a drain, a connection electrode, a first branch portion and a second branch portion. The gate is electrically connected with a scan line. The channel layer located at a side of the gate is electrically isolated from the gate. The source, the drain and the connection electrode are disposed on a part region of the channel layer. The first branch portion disposed on a part region of the channel layer is connected with an end of the connection electrode. The first branch portion surrounds the source located on the channel layer. The second branch portion disposed on a part region of the channel layer is connected with the other end of the connection electrode. The second branch portion surrounds the drain located on the channel layer.

Abstract: A UV sensor comprises a silicon-rich dielectric layer with a refractive index in a range of about 1.7 to about 2.5 for serving as the light sensing material of the UV sensor. The fabrication method of the UV sensor can be integrated with the fabrication process of semiconductor devices or flat display panels.

Abstract: A reflective type touch-sensing display panel including a front substrate, scan lines, data lines, pixel structures, photo-sensors, readout devices, a rear substrate and a reflective display medium is provided. The front substrate has an inner surface. The scan lines and the data lines are on the inner surface of the front substrate and intersected to each other. The pixel structures are disposed on the inner surface of the front substrate, and each pixel structure is electrically connected to one of the scan lines and one of the data lines correspondingly. The photo-sensors are disposed on the inner surface of the front substrate. Each readout device is electrically connected to one of the photo-sensor correspondingly. The rear substrate is disposed opposite to the front substrate. The reflective display medium is sealed between the front substrate and the rear substrate.

Abstract: An array substrate and method for manufacturing the same is provided, wherein a data line is composed of first and second segments connected by a contact pad. First and second insulation layers are disposed between the first segment of the data line and a shielding electrode. In addition, the first insulation layer is disposed between the second segment of the data line and a gate line in their overlapping area. Accordingly, the coupling effect between the conductive layers can be reduced. For example, the RC delay problem due to parasitic capacitance between the shielding electrode and the data line is solved. As a result of the design of the two insulator layers between the first segment of the data line and the shielding electrode, the shorting between the conductive layers can also be simultaneously solved and the product yield can be increased.

Abstract: A flexible liquid crystal display panel and method for manufacturing the same are provided. The flexible liquid crystal display panel includes a rigid substrate, a flexible substrate and a liquid crystal layer disposed therebetween.

Abstract: A thin film transistor (TFT) and a fabricating method thereof are provided. The TFT includes a channel layer, an ohmic contact layer, a dielectric layer, a source, a drain, a gate, and a gate insulating layer. The channel layer has an upper surface and a sidewall. The ohmic contact layer is disposed on a portion of the upper surface of the channel layer. The dielectric layer is disposed on the sidewall of the channel layer, and does not overlap with the ohmic contact layer. The source and the drain are disposed on portions of the ohmic contact layer and the dielectric layer. A portion of dielectric layer is not covered by the source or the drain. The gate is above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer.

Abstract: An array substrate and method for manufacturing the same is provided, wherein a data line is composed of first and second segments connected by a contact pad. First and second insulation layers are disposed between the first segment of the data line and a shielding electrode. In addition, the first insulation layer is disposed between the second segment of the data line and a gate line in their overlapping area. Accordingly, the coupling effect between the conductive layers can be reduced. For example, the RC delay problem due to parasitic capacitance between the shielding electrode and the data line is solved. As a result of the design of the two insulator layers between the first segment of the data line and the shielding electrode, the shorting between the conductive layers can also be simultaneously solved and the product yield can be increased.

Abstract: In one aspect of this invention, a pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode having a first portion and a second portion extending from the first portion, and formed over the scan line, the data line and the switch, where the first portion is overlapped with the switch and the second portion is overlapped with the data line, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode in the pixel area, where the first portion is overlapped with the first portion of the shielding electrode so as to define a storage capacitor therebetween and the second portion has no overlapping with the second portion of the shielding electrode.

Abstract: A thin film transistor (TFT) and a fabricating method thereof are provided. The TFT includes a channel layer, an ohmic contact layer, a dielectric layer, a source, a drain, a gate, and a gate insulating layer. The channel layer has an upper surface and a sidewall. The ohmic contact layer is disposed on a portion of the upper surface of the channel layer. The dielectric layer is disposed on the sidewall of the channel layer, and does not overlap with the ohmic contact layer. The source and the drain are disposed on portions of the ohmic contact layer and the dielectric layer. A portion of dielectric layer is not covered by the source or the drain. The gate is above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer.

Abstract: An electrophoresis display panel including an active device array substrate and an electrophoresis display film is provided. The active device array substrate includes a plurality of active devices and a shielding pattern. The electrophoresis display film is disposed on the active device array substrate. The electrophoresis display film includes a conductive layer, a dielectric layer and a plurality of electrophoresis display mediums. The dielectric layer is disposed on the conductive layer and has a plurality of micro-cups arranged in area array. The dielectric layer is between the conductive layer and the active device array substrate. Light passing through the dielectric layer is prevented from irradiating onto the active devices by the shielding pattern. In addition, the electrophoresis display mediums are filled within the micro-cups, respectively.

Abstract: A fabrication method of a touch panel is provided. In the fabrication method, the two substrates are provided, and a plurality of touch units are formed on each of the substrates. A sealant and a plurality of first spacers are provided between the substrates, and the substrates are bonded through the sealant, so that the touch units are sealed between the substrates. The touch units and the first spacers are surrounded by the sealant. The substrates are thinned. The thinned substrates are cut into a plurality of sub-mounts separated from one another. Each of the sub-mounts has one of the touch units thereon.

Abstract: A touch panel includes an insulating base, a plurality of first sensing electrodes, a plurality of second sensing electrodes and a plurality of third sensing electrodes. The insulating base has a first surface and a second surface. The first sensing electrodes and the second sensing electrodes are disposed on the first surface of the insulating base, and electrically isolated from each other. The third sensing electrodes are disposed on the second surface of the insulating base, and each third sensing electrode at least partially overlaps a portion of the first sensing electrodes and a portion of the second sensing electrodes.

Abstract: This invention in one aspect relates to a pixel structure. In one embodiment, the pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode having a first portion and a second portion extending from the first portion, and formed over the scan line, the data line and the switch, where the first portion is overlapped with the switch and the second portion is overlapped with the data line, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode in the pixel area, where the first portion is overlapped with the first portion of the shielding electrode so as to define a storage capacitor therebetween and the second portion has no overlapping with the second portion of the shielding electrode.

Abstract: A method for manufacturing an array substrate is provided, wherein a data line is composed of first and second segments connected by a contact pad. First and second insulation layers are disposed between the first segment of the data line and a shielding electrode. In addition, the first insulation layer is disposed between the second segment of the data line and a gate line in their overlapping area. Accordingly, the coupling effect between the conductive layers can be reduced. For example, the RC delay problem due to parasitic capacitance between the shielding electrode and the data line is solved. As a result of the design of the two insulator layers between the first segment of the data line and the shielding electrode, the shorting between the conductive layers can also be simultaneously solved and the product yield can be increased.

Abstract: An electrophoresis display pixel including an electrophoresis display film, a substrate, a first active device, a second active device, a first electrode, and a second electrode is provided. The substrate is disposed on the electrophoresis display film, and the substrate has a transparent region and a non-transparent region. The first active device and the second active device are disposed on the substrate and located in the non-transparent region. The first electrode is disposed on the substrate, located in the transparent region, and electrically connected to the first active device. The second electrode is disposed on the substrate, located in the non-transparent region, and electrically connected to the second active device. A light passes through the transparent region and enters the electrophoresis display film to be displayed. A display apparatus including the abovementioned electrophoresis display pixel is also provided.

Abstract: An embedded touch display panel including a first substrate and a second substrate is provided. The first substrate having a displaying region and a sensing region includes a stack structure, a first conductive layer and a first alignment layer. The stack structure disposed on the first substrate within the sensing region includes a protruding structure and a first rough structure disposed on the protruding structure. The first conductive layer conformally disposed on the stack structure has a first rough surface. The first rough surface is exposed from the first alignment layer that covers the first conductive layer. The second substrate includes a second conductive layer and a second alignment layer. The second conductive layer whose position corresponds to the sensing region is disposed on the second structure. A portion of the second conductive layer corresponding to the first rough surface is exposed from the second alignment layer covering thereon.

Abstract: A bottom gate thin film transistor and an active array substrate are provided. The bottom gate thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a plurality of sources and a plurality of drains. The gate insulation layer is disposed on the gate. The semiconductor layer is disposed on the gate insulation layer and located above the gate. An area ratio of the semiconductor layer and the gate is about 0.001 to 0.9. The sources are electrically connected with each other, and the drains are electrically connected with each other.

Abstract: A touch display panel including a first substrate, a second substrate and a liquid crystal layer is provided. The first substrate includes sensing areas and a non-sensing area outside the sensing areas. Each sensing area is provided with a first electrode thereon. The second substrate includes main spacers, sensing protrusions, first sub-spacers and second sub-spacers. The main spacers are connected to the non-sensing area. The sensing protrusions are corresponding to the sensing area and respectively have a second electrode. A sensing gap exists between each second electrode and the corresponding first electrode. The first sub-spacers are corresponding to the non-sensing area and respectively keep a first sub-spacer gap from the first substrate. The second sub-spacers are corresponding to the non-sensing area and respectively keep a second sub-spacer gap from the first substrate. The sensing gap is greater than the first sub-spacer gap and less than the second sub-spacer gap.

Abstract: The present invention in one aspect relates to a solar cell formed on a substrate, a bottom electrode member formed on the solar cell, an electrophoretic display panel formed on the bottom electrode member, having a plurality of electrophoretic cell structures spatially arranged in a matrix form, each electrophoretic cell structure containing a plurality of charged particles movable in the electrophoretic cell structure responsively to applied fields, and a top electrode member formed on the electrophoretic display panel, where at least one of the bottom electrode member and the top electrode member includes a plurality of in-plane switching (IPS) electrodes. Each IPS electrode is positioned in relation to a corresponding electrophoretic cell structure for controlling movements of the charged particles therein along a horizontal direction parallel to the electrophoretic display panel.

Abstract: A method for manufacturing a non-volatile memory and a structure thereof are provided. The manufacturing method comprises the following steps. Firstly, a substrate is provided. Next, a semiconductor layer is formed on the substrate. Then, a Si-rich dielectric layer is formed on the semiconductor layer. After that, a plurality of silicon nanocrystals is formed in the Si-rich dielectric layer by a laser annealing process to form a charge-storing dielectric layer. Last, a gate electrode is formed on the charge-storing dielectric layer.