Abstract: A method of making a semiconductor device includes forming a first polysilicon structure over a first portion of a substrate. The method further includes forming a first spacer on a sidewall of the first polysilicon structure, wherein the first spacer has a concave corner region between an upper portion and a lower portion. The method further includes forming a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer has a first thickness over the concave corner region and a second thickness over the first polysilicon structure, and a difference between the first thickness and the second thickness is at most 10% of the second thickness.

Abstract: A method includes, in response to receiving an incoming service request and establishing a call chain of pods of a service mesh network, setting a retry locker parameter to a locked state for each pod in the call chain. A locked retry locker parameter prevents the pod from initiating retries of a service request. The method includes, in response to determining that a pod in the call chain is unavailable, setting the retry locker parameter to an unlocked state for a previous pod just prior to the pod that is unavailable. The unlocked state allows a retry to the pod that is unavailable. In response to the previous pod reaching a retry limit, the method includes setting the retry locker parameter to unlocked for each pod in the call chain and sending a service termination message to a service requester.

Abstract: A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.

Abstract: A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

Abstract: The present disclosure provides a near-eye display device and a construction method for a meta lens. The near-eye display device includes a substrate (10), a meta lens array (40) provided on the side of the substrate (10) close to an eye (100), and a pixel island array (30) located on the side of the substrate (10) away from the eye (100). The pixel island array (30) includes a plurality of pixel islands. The meta lens array (40) includes a plurality of meta lenses. The orthographic projection of the lens center of the meta lens on the substrate (10) overlaps the orthographic projection of the pixel center of the pixel island on the substrate. The lens center is the geometric center of the meta lens, and the pixel center is the geometric center of the pixel island.

Abstract: An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.

Abstract: A connecting structure includes a first dielectric layer, a first connecting via in the first dielectric layer, a second connecting via in the first dielectric layer, and an isolation between the first connecting via and the second connecting via. The isolation separates the first and second connecting vias from each other. The first connecting via, the isolation and the second connecting via are line symmetrical about a central line perpendicular to a top surface of the first dielectric layer.

Abstract: The present invention relates to compositions comprising polypeptides having xylanase activity and polypeptides having arabinofuranosidase activity for use in, e.g., animal feed. The present invention further relates to polypeptides having arabinofuranosidase activity, polypeptides having xylanase activity and polynucleotides encoding the polypeptides. The invention also relates to nucleic acid constructs, vectors, and host cells comprising the polynucleotides as well as methods of producing and using the polypeptides.

Abstract: In some embodiments, a semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.

Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of first metal strips extending in a first direction on a first plane; and forming a plurality of second metal strips extending in the first direction on a second plane over the first plane by executing a photolithography operation with a single mask, wherein a first second metal strip (FIG. 1, 131) is disposed over a first first metal strip; wherein the first first metal strip and the first second metal strip are directed to a first voltage source; wherein a distance between the first second metal strip and a second second metal strip immediate adjacent to the first second metal strip is greater than a distance between the second second metal strip and a third second metal strip immediate adjacent to the second second metal strip.

Abstract: A motor control apparatus receives a DC power source through a DC terminal and is coupled to a motor. The motor control apparatus includes a brake, an inverter, and a controller. The brake is coupled to the inverter. The brake includes an energy-consuming component and a switch component. The controller controls the inverter to convert the DC power source to drive the motor. When the controller determines that the DC power source is interrupted, the controller stops controlling the inverter, and the switch component is self-driven turned on so that a back electromotive force generated by the motor is consumed through the energy-consuming component.

Abstract: Provided is a method for compensating a displayed picture in a display screen. The display screen includes a plurality of regions, each of the plurality of regions including a plurality of pixels; the method includes: determining transformation matrices corresponding to pixels in the plurality of regions based on texture complexities of pictures to be displayed in the plurality of regions; acquiring compensated grayscales by compensating grayscales of pixel points in the pictures to be displayed in the plurality of regions based on the transformation matrices corresponding to the pixels in the plurality of regions.

Abstract: A display substrate and a display device. The display substrate includes a pixel circuit in which the driving circuit controls a driving current for driving the light emitter element to emit light; the first light emission control circuit applies a first voltage to a first terminal of the driving circuit in response to a first light emission control signal; the second light emission control circuit applies the driving current to the light emitter element in response to a second light emission control signal; the first reset circuit applies a first reset voltage to the control terminal of the driving circuit in response to a first reset signal; the first reset signal and the first light emission control signal are simultaneously turn-on signals during a period; the first light emission control line and the second light emission control line extend along a first direction and are arranged in a second direction.

Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of gate strips, each gate strip is a gate terminal of a transistor; forming a plurality of first contact vias connected to a part of the gate strips; forming a plurality of first metal strips above the plurality of gate strips; connecting one of the first metal strips to one of the first contact vias; forming a plurality of second metal strips above the plurality of first metal strips, wherein the plurality of second metal strips are co-planar, each second metal strip and one of the first metal strips are crisscrossed from top view; a length between two adjacent gate strips is twice as a length between two adjacent second metal strips, and a length of said one of the first metal strips is smaller than two and a half times as the length between two adjacent gate strips.

Abstract: A semiconductor structure includes: a first gate structure and a second gate structure extending in a first direction; a first base level metal interconnect (M0) pattern extending in a second direction perpendicular to the first direction; a second M0 pattern extending in the second direction; a third M0 pattern located between the first and second gate structures and extending in the first direction, two ends of the third M0 pattern connected to the first M0 pattern and the second M0 pattern, respectively; a fourth M0 pattern and a fifth M0 pattern located between the first and second M0 patterns and extending in the second direction. A distance between the fourth M0 pattern and the first M0 pattern in the first direction is equal to a minimum M0 pattern pitch, and a distance between the fourth M0 pattern and the second M0 pattern is equal to the minimum M0 pattern pitch.

Abstract: A patch antenna includes a plurality of patch units, a first feeding branch, and a second feeding branch. The plurality of patch units is symmetric relative to a virtual symmetry axis. The plurality of patch units is arranged at intervals. A gap is formed between adjacent patch units, and the adjacent patch units are coupled through the gap. The first feeding branch and the second feeding branch are symmetric relative to the symmetry axis, and each of the first feeding branch and the second feeding branch is electrically connected to at least one patch unit of the plurality of patch units. The first feeding branch is configured for a first polarization of the patch antenna, and the second feeding branch is configured for a second polarization of the patch antenna.

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.

Abstract: The present invention discloses compounds of Formula (I), and pharmaceutically acceptable salts, thereof: which inhibit coronavirus replication activity. The invention further relates to pharmaceutical compositions comprising a compound of Formula (I) or a pharmaceutically acceptable salt thereof, and methods of treating or preventing a coronavirus infection in a subject in need thereof, comprising administering to the subject a therapeutically effective amount of a compound of Formula (I) or a pharmaceutically acceptable salt thereof.

Abstract: A semiconductor structure includes: a first gate structure and a second gate structure extending in a first direction; a first base level metal interconnect (M0) pattern extending in a second direction perpendicular to the first direction; a second M0 pattern extending in the second direction; a third M0 pattern located between the first and second gate structures and extending in the first direction, two ends of the third M0 pattern connected to the first M0 pattern and the second M0 pattern, respectively; a fourth M0 pattern and a fifth M0 pattern located between the first and second M0 patterns and extending in the second direction. A distance between the fourth M0 pattern and the first M0 pattern in the first direction is equal to a minimum M0 pattern pitch, and a distance between the fourth M0 pattern and the second M0 pattern is equal to the minimum M0 pattern pitch.