Abstract: An equalization circuit and an equalization method implemented thereby are provided. A received symbol is received to generate a equalizer output. In the equalization circuit, an equalizer performs equalization to the received symbol based on a SNR value of the equalizer output. A SNR estimator coupled to the output of equalizer receives the equalizer output to measure the SNR value. The equalizer equalizes the received symbol by the LMS algorithm in which coefficients are recursively updated by a step size, and the step size is adjusted based on the SNR value.

Abstract: A decoding apparatus and method are described. The decoder includes N successive decoder groups numbered 1 to N arranged in series. Each decoder group includes primary decoding means for decoding the first sequence of codewords in combination with the source sequence of symbols to produce a sequence of primary decoded symbols; intermediate interleaving means for interleaving the sequence of primary decoded symbols using intra-block permutations on the source sequence of symbols and inter-block permutations on each intra-block permuted block across the predetermined number of the intra-block permuted blocks to produce a sequence of intermediate symbols; secondary decoding means for decoding the second sequence of codewords in combination with the sequence of intermediate symbols and a sequence of interleaved source symbols to produce a sequence of secondary decoded symbols; and de-interleaving means for de-interleaving the sequence of secondary decoded symbols to produce a sequence of estimated symbols.

Abstract: A system, a multi-stage equalizer and a method for generating an equalized signal in response to a received signal are provided. The multi-stage equalizer comprises a first DFE, and a second DFE. The first DFE generates a first signal in response to the received signal. The second DFE generates a second signal in response to the first signal, subtracts the second signal from a third signal to generate a fourth signal, and generates the equalized signal in response to the fourth signal, wherein the fourth signal is an unsliced signal. The method comprises steps of: providing a first DFE to generate a first signal in response to the received signal; providing a second DFE to generate a second signal in response to the first signal and to subtract the second signal from a third signal to generate a fourth signal; and generating the equalized signal in response to the fourth signal.

Abstract: An integrated control circuit for a resonant power converter includes a minimum-frequency programming circuit connected a first resistor to program a minimum switching frequency of the power converter. A feedback circuit is coupled to a feedback terminal to receive a feedback signal for generating an adjustment signal. A maximum-frequency programming circuit connects a second resistor to determine a maximum switching frequency in response to the adjustment signal. An oscillator is coupled to the minimum-frequency programming circuit and the maximum-frequency programming circuit to generate an oscillation signal for determining the switching frequency of the power converter. A feed-forward circuit is connected to a feed-forward terminal to receive a feed-forward signal represents the input voltage of the power converter. The switching frequency is increased in response to decrease of the feedback signal, and the switching frequency is increased in response to the increase of the feed-forward signal.

Abstract: A digital television receiver includes a tuner for down-converting an incoming signal to produce a down-converted signal according to a local oscillator signal corresponding to a selected channel. A filter is coupled to the tuner for filtering the down-converted signal to produce an intermediate frequency (IF) signal. A carrier recovery unit is coupled to the filter for locking to a carrier frequency of the IF signal, and a pre-shift unit is coupled to the tuner. By shifting the local oscillator signal in a first direction by a predetermined first frequency shift in a first phase of carrier recovery, and then by shifting the local oscillator signal in a second direction by a second frequency shift in a second phase of carrier recovery, the pre-shift unit ensures a pilot tone of a selected channel is not filtered from the down-converted signal by the filter.

Abstract: A method and apparatus for rejecting an interference signal from an input frequency spectrum. The method includes the steps of receiving the input signal; frequency-shifting the received input signal by a first frequency-shifting amount; and filtering the frequency-shifted input signal to filter out the interference component from the input signal.

Abstract: A mouse and pad assembly includes a pad member; and a mouse member, which is arranged on top of and connected to the pad member in such a way as to be angularly and linearly displaceable relative to the pad member; the mouse member has several buttons on an upper side thereof, and it has a sensor device facing the pad member for sensing movement of the mouse member relative to the pad member.

Abstract: A carrier recovery system includes an in-phase mixer for mixing an incoming signal with an in-phase reference signal to produce an in-phase baseband signal; a quadrature-phase mixer for mixing the incoming signal with a quadrature-phase reference signal to produce a quadrature-phase baseband signal; a DC detector for measuring a DC offset of the quadrature-phase baseband signal; and a frequency synthesizer for generating the in-phase reference signal and the quadrature-phase reference signal according to the DC offset measured by the DC detector. The quadrature-phase reference signal is the in-phase reference signal phase-delayed by ninety degrees. The DC offset of the quadrature-phase baseband signal is caused by a pilot tone of the VSB signal for a selected carrier in an Advanced Television Systems Committee (ATSC) digital television (DTV) receiver. By minimizing the DC offset, the carrier recover system locks the quadrature-phase reference signal and the in-phase reference signal to the selected channel.

Abstract: A digital television receiver includes a tuner for down-converting an incoming signal to produce a down-converted signal according to a local oscillator signal corresponding to a selected channel. A filter is coupled to the tuner for filtering the down-converted signal to produce an intermediate frequency (IF) signal. A carrier recovery unit is coupled to the filter for locking to a carrier frequency of the IF signal, and a pre-shift unit is coupled to the tuner. By shifting the local oscillator signal in a first direction by a predetermined first frequency shift in a first phase of carrier recovery, and then by shifting the local oscillator signal in a second direction by a second frequency shift in a second phase of carrier recovery, the pre-shift unit ensures a pilot tone of a selected channel is not filtered from the down-converted signal by the filter.

Abstract: An interference detecting circuit for use in an ATSC system and for detecting interference of an ATSC signal includes: a buffering module for delaying to output a first PN63 synchronization format data when receiving the first PN63 synchronization format data; a correlation arithmetic circuit coupled to the buffering module for receiving the ATSC signal and performing a correlation operation on a second PN63 synchronization format data and the delayed first PN63 synchronization format data to output a detection signal when receiving the second PN63 synchronization format data; and a determining circuit for determining whether performing interference rejection on the ATSC signal or not according to the result of the above-mentioned correlation operation.

Abstract: A synchronization signal detector includes: a first circuit configured to delay the data signal by a period of at least one data segment of the data signal to generate a delayed signal; a second circuit configured to produce a plurality of similarity signals according to the data signal and the delayed signal, each of the similarity signals representing the similarity between the data signal and the delayed signal, and a third circuit configured to determine the synchronization signal of the data signal according to the similarity signals. The present invention further provides a method corresponding to the signal detector.

Abstract: An interleaver and method of interleaving operate on data represented in a sequence of symbols to produce an interleaved sequence of symbols. The interleaver performs intra-block and inter-block permutations on the sequence of symbols. An encoder and method of encoding operate on data represented in a source sequence of symbols. The source sequence of symbols is encoded into a first sequence of codewords and interleaved using intra-block and inter-block permutations to produce a sequence of interleaved symbols. The sequence of interleaved symbols is encoded into a second sequence of codewords. A decoder and method of decoding operate on data represented in a sequence of received symbols. The sequence of received symbols comprises a formatted copy of the source sequence of symbols and the first and the second sequence of codewords.

Abstract: An interleaver and method of interleaving operate on data represented in a sequence of symbols to produce an interleaved sequence of symbols. The interleaver performs intra-block and inter-block permutations on the sequence of symbols. An encoder and method of encoding operate on data represented in a source sequence of symbols. The source sequence of symbols is encoded into a first sequence of codewords and interleaved using intra-block and inter-block permutations to produce a sequence of interleaved symbols. The sequence of interleaved symbols is encoded into a second sequence of codewords. A decoder and method of decoding operate on data represented in a sequence of received symbols. The sequence of received symbols comprises a formatted copy of the source sequence of symbols and the first and the second sequence of codewords.

Abstract: An interleaver and method of interleaving operate on data represented in a sequence of symbols to produce an interleaved sequence of symbols. The interleaver performs intra-block and inter-block permutations on the sequence of symbols. An encoder and method of encoding operate on data represented in a source sequence of symbols. The source sequence of symbols is encoded into a first sequence of codewords and interleaved using intra-block and inter-block permutations to produce a sequence of interleaved symbols. The sequence of interleaved symbols is encoded into a second sequence of codewords. A decoder and method of decoding operate on data represented in a sequence of received symbols. The sequence of received symbols comprises a formatted copy of the source sequence of symbols and the first and the second sequence of codewords.

Abstract: An interleaver and method of interleaving operate on data represented in a sequence of symbols to produce an interleaved sequence of symbols. The interleaver performs intra-block and inter-block permutations on the sequence of symbols. An encoder and method of encoding operate on data represented in a source sequence of symbols. The source sequence of symbols is encoded into a first sequence of codewords and interleaved using intra-block and inter-block permutations to produce a sequence of interleaved symbols. The sequence of interleaved symbols is encoded into a second sequence of codewords. A decoder and method of decoding operate on data represented in a sequence of received symbols. The sequence of received symbols comprises a formatted copy of the source sequence of symbols and the first and the second sequence of codewords.